3D VLSI Non-Slicing Floor Planning using Modified Corner List Representation Article Swipe
YOU?
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· 2015
· Open Access
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· DOI: https://doi.org/10.17485/ijst/2015/v8i35/81204
Background: Floorplanning is important step in physical design automation of VLSI circuits, because it gives an early feedback on the architectural design. It is the process of finding the position of the module such that no two modules overlap with each other. Methods: In order to have an efficient floorplan, the total area occupied by the modules should be minimum. So, non-slicing floorplan is used to find an optimal floorplan layout. To represent non-slicing floorplan, a number of representations are proposed. Findings: To encompass billions of transistors in an Integrated Circuit (IC), 3Dimensional (3D) IC is preferred instead of 2D. In this paper, a novel 3Dimensional (3D) non-slicing floorplanning representation called Modified Corner List (MCL) algorithm is proposed and properties of MCL algorithm is derived. The proposed algorithm is illustrated using Microelectronics Centre of North Carolina (MCNC) benchmark circuits and simulation results shows that it is very effective for 3D floorplan representation. Improvements: The proposed algorithm works well for small number of modules. As the number of module increases, computational time taken by the algorithm also increases. The above problem can be solved by applying heuristic algorithm in association with MCL strategy to find near optimal placement in reduced run time.Keywords: MCNC Benchmark Circuits, Modified Corner List, 3D Non-Slicing Floorplan, VLSI
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- Type
- article
- Language
- en
- Landing Page
- https://doi.org/10.17485/ijst/2015/v8i35/81204
- http://www.indjst.org/index.php/indjst/article/download/81204/65468
- OA Status
- diamond
- Cited By
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- OpenAlex ID
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https://openalex.org/W2198836535Canonical identifier for this work in OpenAlex
- DOI
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https://doi.org/10.17485/ijst/2015/v8i35/81204Digital Object Identifier
- Title
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3D VLSI Non-Slicing Floor Planning using Modified Corner List RepresentationWork title
- Type
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articleOpenAlex work type
- Language
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enPrimary language
- Publication year
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2015Year of publication
- Publication date
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2015-12-28Full publication date if available
- Authors
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P. Sivaranjani, A. Senthil KumarList of authors in order
- Landing page
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https://doi.org/10.17485/ijst/2015/v8i35/81204Publisher landing page
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https://www.indjst.org/index.php/indjst/article/download/81204/65468Direct link to full text PDF
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YesWhether a free full text is available
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diamondOpen access status per OpenAlex
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https://www.indjst.org/index.php/indjst/article/download/81204/65468Direct OA link when available
- Concepts
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Floorplan, Very-large-scale integration, Computer science, Slicing, Benchmark (surveying), Algorithm, Physical design, Representation (politics), Integrated circuit layout, Heuristic, Integrated circuit, Routing (electronic design automation), Computer engineering, Parallel computing, Circuit design, Embedded system, Artificial intelligence, Politics, Geodesy, Geography, Operating system, Law, World Wide Web, Political scienceTop concepts (fields/topics) attached by OpenAlex
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3Total citation count in OpenAlex
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2021: 1, 2016: 2Per-year citation counts (last 5 years)
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15Number of works referenced by this work
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10Other works algorithmically related by OpenAlex
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