A Microprocessor Protection Architecture against Hardware Trojans in Memories Article Swipe
Alperen Bolat
,
Luca Cassano
,
Pedro Reviriego
,
Oğuz Ergin
,
Marco Ottavi
·
YOU?
·
· 2020
· Open Access
·
· DOI: https://doi.org/10.1109/dtis48698.2020.9080961
YOU?
·
· 2020
· Open Access
·
· DOI: https://doi.org/10.1109/dtis48698.2020.9080961
Software exploitable Hardware Trojan Horses (HWTs) have been currently inserted in commercial CPUs and, very recently, in memories. Such attacks may allow malicious users to run their own software or to gain unauthorized privileges over the system. Therefore, HWTs are nowadays considered a serious threat both from academy and industry. This paper presents a protection architecture meant to shield the communication between the CPU and the memory in a microprocessor-based system. The architecture aims at detecting the activation on HWTs infesting the instruction and data memories of the system. Our proposal relies on the use of Bloom Filters (BFs) that are included in ad-hoc designed checkers and integrated in the protection architecture. BFs guarantee zero false alarms and a small (and configurable) percentage of undetected alarms. We applied the protection architecture to a case study system based on a RISC-V microprocessor implemented on an FPGA and running a set of software benchmarks. Our proposal demonstrated to be able to detect more than 99% of possible HWTs activations with zero false alarms. We measured a lookup table overhead ranging from 0.68% up to 10.52% and a Hip-Hop overhead between 0.68% and 0.99%, and with no working frequency reduction.
Related Topics
Concepts
Metadata
- Type
- article
- Language
- en
- Landing Page
- https://doi.org/10.1109/dtis48698.2020.9080961
- OA Status
- green
- Cited By
- 18
- References
- 33
- Related Works
- 10
- OpenAlex ID
- https://openalex.org/W3022895293
All OpenAlex metadata
Raw OpenAlex JSON
- OpenAlex ID
-
https://openalex.org/W3022895293Canonical identifier for this work in OpenAlex
- DOI
-
https://doi.org/10.1109/dtis48698.2020.9080961Digital Object Identifier
- Title
-
A Microprocessor Protection Architecture against Hardware Trojans in MemoriesWork title
- Type
-
articleOpenAlex work type
- Language
-
enPrimary language
- Publication year
-
2020Year of publication
- Publication date
-
2020-04-01Full publication date if available
- Authors
-
Alperen Bolat, Luca Cassano, Pedro Reviriego, Oğuz Ergin, Marco OttaviList of authors in order
- Landing page
-
https://doi.org/10.1109/dtis48698.2020.9080961Publisher landing page
- Open access
-
YesWhether a free full text is available
- OA status
-
greenOpen access status per OpenAlex
- OA URL
-
https://hdl.handle.net/11311/1150440Direct OA link when available
- Concepts
-
Computer science, Embedded system, Microprocessor, Overhead (engineering), Memory protection, Field-programmable gate array, Architecture, Software, Operating system, Computer hardware, Memory management, Virtual memory, Semiconductor memory, Art, Visual artsTop concepts (fields/topics) attached by OpenAlex
- Cited by
-
18Total citation count in OpenAlex
- Citations by year (recent)
-
2025: 1, 2024: 2, 2023: 4, 2022: 7, 2021: 4Per-year citation counts (last 5 years)
- References (count)
-
33Number of works referenced by this work
- Related works (count)
-
10Other works algorithmically related by OpenAlex
Full payload
| id | https://openalex.org/W3022895293 |
|---|---|
| doi | https://doi.org/10.1109/dtis48698.2020.9080961 |
| ids.doi | https://doi.org/10.1109/dtis48698.2020.9080961 |
| ids.mag | 3022895293 |
| ids.openalex | https://openalex.org/W3022895293 |
| fwci | 3.76595981 |
| type | article |
| title | A Microprocessor Protection Architecture against Hardware Trojans in Memories |
| biblio.issue | |
| biblio.volume | |
| biblio.last_page | 6 |
| biblio.first_page | 1 |
| topics[0].id | https://openalex.org/T12122 |
| topics[0].field.id | https://openalex.org/fields/17 |
| topics[0].field.display_name | Computer Science |
| topics[0].score | 1.0 |
| topics[0].domain.id | https://openalex.org/domains/3 |
| topics[0].domain.display_name | Physical Sciences |
| topics[0].subfield.id | https://openalex.org/subfields/1708 |
| topics[0].subfield.display_name | Hardware and Architecture |
| topics[0].display_name | Physical Unclonable Functions (PUFs) and Hardware Security |
| topics[1].id | https://openalex.org/T11424 |
| topics[1].field.id | https://openalex.org/fields/17 |
| topics[1].field.display_name | Computer Science |
| topics[1].score | 0.9932000041007996 |
| topics[1].domain.id | https://openalex.org/domains/3 |
| topics[1].domain.display_name | Physical Sciences |
| topics[1].subfield.id | https://openalex.org/subfields/1702 |
| topics[1].subfield.display_name | Artificial Intelligence |
| topics[1].display_name | Security and Verification in Computing |
| topics[2].id | https://openalex.org/T10502 |
| topics[2].field.id | https://openalex.org/fields/22 |
| topics[2].field.display_name | Engineering |
| topics[2].score | 0.9846000075340271 |
| topics[2].domain.id | https://openalex.org/domains/3 |
| topics[2].domain.display_name | Physical Sciences |
| topics[2].subfield.id | https://openalex.org/subfields/2208 |
| topics[2].subfield.display_name | Electrical and Electronic Engineering |
| topics[2].display_name | Advanced Memory and Neural Computing |
| is_xpac | False |
| apc_list | |
| apc_paid | |
| concepts[0].id | https://openalex.org/C41008148 |
| concepts[0].level | 0 |
| concepts[0].score | 0.7239354252815247 |
| concepts[0].wikidata | https://www.wikidata.org/wiki/Q21198 |
| concepts[0].display_name | Computer science |
| concepts[1].id | https://openalex.org/C149635348 |
| concepts[1].level | 1 |
| concepts[1].score | 0.6778637766838074 |
| concepts[1].wikidata | https://www.wikidata.org/wiki/Q193040 |
| concepts[1].display_name | Embedded system |
| concepts[2].id | https://openalex.org/C2780728072 |
| concepts[2].level | 2 |
| concepts[2].score | 0.5865041017532349 |
| concepts[2].wikidata | https://www.wikidata.org/wiki/Q5297 |
| concepts[2].display_name | Microprocessor |
| concepts[3].id | https://openalex.org/C2779960059 |
| concepts[3].level | 2 |
| concepts[3].score | 0.5073429942131042 |
| concepts[3].wikidata | https://www.wikidata.org/wiki/Q7113681 |
| concepts[3].display_name | Overhead (engineering) |
| concepts[4].id | https://openalex.org/C18131444 |
| concepts[4].level | 5 |
| concepts[4].score | 0.48081839084625244 |
| concepts[4].wikidata | https://www.wikidata.org/wiki/Q163585 |
| concepts[4].display_name | Memory protection |
| concepts[5].id | https://openalex.org/C42935608 |
| concepts[5].level | 2 |
| concepts[5].score | 0.4799385666847229 |
| concepts[5].wikidata | https://www.wikidata.org/wiki/Q190411 |
| concepts[5].display_name | Field-programmable gate array |
| concepts[6].id | https://openalex.org/C123657996 |
| concepts[6].level | 2 |
| concepts[6].score | 0.46963927149772644 |
| concepts[6].wikidata | https://www.wikidata.org/wiki/Q12271 |
| concepts[6].display_name | Architecture |
| concepts[7].id | https://openalex.org/C2777904410 |
| concepts[7].level | 2 |
| concepts[7].score | 0.4530943036079407 |
| concepts[7].wikidata | https://www.wikidata.org/wiki/Q7397 |
| concepts[7].display_name | Software |
| concepts[8].id | https://openalex.org/C111919701 |
| concepts[8].level | 1 |
| concepts[8].score | 0.43138769268989563 |
| concepts[8].wikidata | https://www.wikidata.org/wiki/Q9135 |
| concepts[8].display_name | Operating system |
| concepts[9].id | https://openalex.org/C9390403 |
| concepts[9].level | 1 |
| concepts[9].score | 0.4070880115032196 |
| concepts[9].wikidata | https://www.wikidata.org/wiki/Q3966 |
| concepts[9].display_name | Computer hardware |
| concepts[10].id | https://openalex.org/C176649486 |
| concepts[10].level | 3 |
| concepts[10].score | 0.23150205612182617 |
| concepts[10].wikidata | https://www.wikidata.org/wiki/Q2308807 |
| concepts[10].display_name | Memory management |
| concepts[11].id | https://openalex.org/C76399640 |
| concepts[11].level | 4 |
| concepts[11].score | 0.1750761866569519 |
| concepts[11].wikidata | https://www.wikidata.org/wiki/Q189401 |
| concepts[11].display_name | Virtual memory |
| concepts[12].id | https://openalex.org/C98986596 |
| concepts[12].level | 2 |
| concepts[12].score | 0.11967676877975464 |
| concepts[12].wikidata | https://www.wikidata.org/wiki/Q1143031 |
| concepts[12].display_name | Semiconductor memory |
| concepts[13].id | https://openalex.org/C142362112 |
| concepts[13].level | 0 |
| concepts[13].score | 0.0 |
| concepts[13].wikidata | https://www.wikidata.org/wiki/Q735 |
| concepts[13].display_name | Art |
| concepts[14].id | https://openalex.org/C153349607 |
| concepts[14].level | 1 |
| concepts[14].score | 0.0 |
| concepts[14].wikidata | https://www.wikidata.org/wiki/Q36649 |
| concepts[14].display_name | Visual arts |
| keywords[0].id | https://openalex.org/keywords/computer-science |
| keywords[0].score | 0.7239354252815247 |
| keywords[0].display_name | Computer science |
| keywords[1].id | https://openalex.org/keywords/embedded-system |
| keywords[1].score | 0.6778637766838074 |
| keywords[1].display_name | Embedded system |
| keywords[2].id | https://openalex.org/keywords/microprocessor |
| keywords[2].score | 0.5865041017532349 |
| keywords[2].display_name | Microprocessor |
| keywords[3].id | https://openalex.org/keywords/overhead |
| keywords[3].score | 0.5073429942131042 |
| keywords[3].display_name | Overhead (engineering) |
| keywords[4].id | https://openalex.org/keywords/memory-protection |
| keywords[4].score | 0.48081839084625244 |
| keywords[4].display_name | Memory protection |
| keywords[5].id | https://openalex.org/keywords/field-programmable-gate-array |
| keywords[5].score | 0.4799385666847229 |
| keywords[5].display_name | Field-programmable gate array |
| keywords[6].id | https://openalex.org/keywords/architecture |
| keywords[6].score | 0.46963927149772644 |
| keywords[6].display_name | Architecture |
| keywords[7].id | https://openalex.org/keywords/software |
| keywords[7].score | 0.4530943036079407 |
| keywords[7].display_name | Software |
| keywords[8].id | https://openalex.org/keywords/operating-system |
| keywords[8].score | 0.43138769268989563 |
| keywords[8].display_name | Operating system |
| keywords[9].id | https://openalex.org/keywords/computer-hardware |
| keywords[9].score | 0.4070880115032196 |
| keywords[9].display_name | Computer hardware |
| keywords[10].id | https://openalex.org/keywords/memory-management |
| keywords[10].score | 0.23150205612182617 |
| keywords[10].display_name | Memory management |
| keywords[11].id | https://openalex.org/keywords/virtual-memory |
| keywords[11].score | 0.1750761866569519 |
| keywords[11].display_name | Virtual memory |
| keywords[12].id | https://openalex.org/keywords/semiconductor-memory |
| keywords[12].score | 0.11967676877975464 |
| keywords[12].display_name | Semiconductor memory |
| language | en |
| locations[0].id | doi:10.1109/dtis48698.2020.9080961 |
| locations[0].is_oa | False |
| locations[0].source | |
| locations[0].license | |
| locations[0].pdf_url | |
| locations[0].version | publishedVersion |
| locations[0].raw_type | proceedings-article |
| locations[0].license_id | |
| locations[0].is_accepted | True |
| locations[0].is_published | True |
| locations[0].raw_source_name | 2020 15th Design & Technology of Integrated Systems in Nanoscale Era (DTIS) |
| locations[0].landing_page_url | https://doi.org/10.1109/dtis48698.2020.9080961 |
| locations[1].id | pmh:oai:art.torvergata.it:2108/259779 |
| locations[1].is_oa | False |
| locations[1].source.id | https://openalex.org/S4306400993 |
| locations[1].source.issn | |
| locations[1].source.type | repository |
| locations[1].source.is_oa | False |
| locations[1].source.issn_l | |
| locations[1].source.is_core | False |
| locations[1].source.is_in_doaj | False |
| locations[1].source.display_name | Cineca Institutional Research Information System (Tor Vergata University) |
| locations[1].source.host_organization | https://openalex.org/I116067653 |
| locations[1].source.host_organization_name | University of Rome Tor Vergata |
| locations[1].source.host_organization_lineage | https://openalex.org/I116067653 |
| locations[1].license | |
| locations[1].pdf_url | |
| locations[1].version | submittedVersion |
| locations[1].raw_type | info:eu-repo/semantics/conferenceObject |
| locations[1].license_id | |
| locations[1].is_accepted | False |
| locations[1].is_published | False |
| locations[1].raw_source_name | |
| locations[1].landing_page_url | http://hdl.handle.net/2108/259779 |
| locations[2].id | pmh:oai:re.public.polimi.it:11311/1150440 |
| locations[2].is_oa | True |
| locations[2].source.id | https://openalex.org/S4306400312 |
| locations[2].source.issn | |
| locations[2].source.type | repository |
| locations[2].source.is_oa | False |
| locations[2].source.issn_l | |
| locations[2].source.is_core | False |
| locations[2].source.is_in_doaj | False |
| locations[2].source.display_name | Virtual Community of Pathological Anatomy (University of Castilla La Mancha) |
| locations[2].source.host_organization | https://openalex.org/I79189158 |
| locations[2].source.host_organization_name | University of Castilla-La Mancha |
| locations[2].source.host_organization_lineage | https://openalex.org/I79189158 |
| locations[2].license | other-oa |
| locations[2].pdf_url | |
| locations[2].version | submittedVersion |
| locations[2].raw_type | info:eu-repo/semantics/conferenceObject |
| locations[2].license_id | https://openalex.org/licenses/other-oa |
| locations[2].is_accepted | False |
| locations[2].is_published | False |
| locations[2].raw_source_name | |
| locations[2].landing_page_url | http://hdl.handle.net/11311/1150440 |
| indexed_in | crossref |
| authorships[0].author.id | https://openalex.org/A5005067066 |
| authorships[0].author.orcid | https://orcid.org/0000-0003-0170-8038 |
| authorships[0].author.display_name | Alperen Bolat |
| authorships[0].countries | TR |
| authorships[0].affiliations[0].institution_ids | https://openalex.org/I13236232 |
| authorships[0].affiliations[0].raw_affiliation_string | TOBB University of Economics and Technology, Turkey |
| authorships[0].institutions[0].id | https://openalex.org/I13236232 |
| authorships[0].institutions[0].ror | https://ror.org/03ewx7v96 |
| authorships[0].institutions[0].type | education |
| authorships[0].institutions[0].lineage | https://openalex.org/I13236232 |
| authorships[0].institutions[0].country_code | TR |
| authorships[0].institutions[0].display_name | TOBB University of Economics and Technology |
| authorships[0].author_position | first |
| authorships[0].raw_author_name | Alperen Bolat |
| authorships[0].is_corresponding | False |
| authorships[0].raw_affiliation_strings | TOBB University of Economics and Technology, Turkey |
| authorships[1].author.id | https://openalex.org/A5007108808 |
| authorships[1].author.orcid | https://orcid.org/0000-0003-3824-7714 |
| authorships[1].author.display_name | Luca Cassano |
| authorships[1].countries | IT |
| authorships[1].affiliations[0].institution_ids | https://openalex.org/I93860229 |
| authorships[1].affiliations[0].raw_affiliation_string | Politecnico di Milano, Italy |
| authorships[1].institutions[0].id | https://openalex.org/I93860229 |
| authorships[1].institutions[0].ror | https://ror.org/01nffqt88 |
| authorships[1].institutions[0].type | education |
| authorships[1].institutions[0].lineage | https://openalex.org/I93860229 |
| authorships[1].institutions[0].country_code | IT |
| authorships[1].institutions[0].display_name | Politecnico di Milano |
| authorships[1].author_position | middle |
| authorships[1].raw_author_name | Luca Cassano |
| authorships[1].is_corresponding | False |
| authorships[1].raw_affiliation_strings | Politecnico di Milano, Italy |
| authorships[2].author.id | https://openalex.org/A5080322790 |
| authorships[2].author.orcid | https://orcid.org/0000-0003-2540-5234 |
| authorships[2].author.display_name | Pedro Reviriego |
| authorships[2].countries | ES |
| authorships[2].affiliations[0].institution_ids | https://openalex.org/I50357001 |
| authorships[2].affiliations[0].raw_affiliation_string | Universidad Carlos III de Madrid, Spain |
| authorships[2].institutions[0].id | https://openalex.org/I50357001 |
| authorships[2].institutions[0].ror | https://ror.org/03ths8210 |
| authorships[2].institutions[0].type | education |
| authorships[2].institutions[0].lineage | https://openalex.org/I50357001 |
| authorships[2].institutions[0].country_code | ES |
| authorships[2].institutions[0].display_name | Universidad Carlos III de Madrid |
| authorships[2].author_position | middle |
| authorships[2].raw_author_name | Pedro Reviriego |
| authorships[2].is_corresponding | False |
| authorships[2].raw_affiliation_strings | Universidad Carlos III de Madrid, Spain |
| authorships[3].author.id | https://openalex.org/A5052707216 |
| authorships[3].author.orcid | https://orcid.org/0000-0003-2701-3787 |
| authorships[3].author.display_name | Oğuz Ergin |
| authorships[3].countries | TR |
| authorships[3].affiliations[0].institution_ids | https://openalex.org/I13236232 |
| authorships[3].affiliations[0].raw_affiliation_string | TOBB University of Economics and Technology, Turkey |
| authorships[3].institutions[0].id | https://openalex.org/I13236232 |
| authorships[3].institutions[0].ror | https://ror.org/03ewx7v96 |
| authorships[3].institutions[0].type | education |
| authorships[3].institutions[0].lineage | https://openalex.org/I13236232 |
| authorships[3].institutions[0].country_code | TR |
| authorships[3].institutions[0].display_name | TOBB University of Economics and Technology |
| authorships[3].author_position | middle |
| authorships[3].raw_author_name | Oguz Ergin |
| authorships[3].is_corresponding | False |
| authorships[3].raw_affiliation_strings | TOBB University of Economics and Technology, Turkey |
| authorships[4].author.id | https://openalex.org/A5048232172 |
| authorships[4].author.orcid | https://orcid.org/0000-0002-5064-7342 |
| authorships[4].author.display_name | Marco Ottavi |
| authorships[4].countries | IT |
| authorships[4].affiliations[0].institution_ids | https://openalex.org/I116067653 |
| authorships[4].affiliations[0].raw_affiliation_string | University of Rome Tor Vergata, Italy |
| authorships[4].institutions[0].id | https://openalex.org/I116067653 |
| authorships[4].institutions[0].ror | https://ror.org/02p77k626 |
| authorships[4].institutions[0].type | education |
| authorships[4].institutions[0].lineage | https://openalex.org/I116067653 |
| authorships[4].institutions[0].country_code | IT |
| authorships[4].institutions[0].display_name | University of Rome Tor Vergata |
| authorships[4].author_position | last |
| authorships[4].raw_author_name | Marco Ottavi |
| authorships[4].is_corresponding | False |
| authorships[4].raw_affiliation_strings | University of Rome Tor Vergata, Italy |
| has_content.pdf | False |
| has_content.grobid_xml | False |
| is_paratext | False |
| open_access.is_oa | True |
| open_access.oa_url | http://hdl.handle.net/11311/1150440 |
| open_access.oa_status | green |
| open_access.any_repository_has_fulltext | False |
| created_date | 2025-10-10T00:00:00 |
| display_name | A Microprocessor Protection Architecture against Hardware Trojans in Memories |
| has_fulltext | False |
| is_retracted | False |
| updated_date | 2025-11-06T03:46:38.306776 |
| primary_topic.id | https://openalex.org/T12122 |
| primary_topic.field.id | https://openalex.org/fields/17 |
| primary_topic.field.display_name | Computer Science |
| primary_topic.score | 1.0 |
| primary_topic.domain.id | https://openalex.org/domains/3 |
| primary_topic.domain.display_name | Physical Sciences |
| primary_topic.subfield.id | https://openalex.org/subfields/1708 |
| primary_topic.subfield.display_name | Hardware and Architecture |
| primary_topic.display_name | Physical Unclonable Functions (PUFs) and Hardware Security |
| related_works | https://openalex.org/W39373273, https://openalex.org/W2098026815, https://openalex.org/W2390545901, https://openalex.org/W2351709090, https://openalex.org/W2111241003, https://openalex.org/W2735012529, https://openalex.org/W2732121450, https://openalex.org/W1604566864, https://openalex.org/W2357771869, https://openalex.org/W4384154458 |
| cited_by_count | 18 |
| counts_by_year[0].year | 2025 |
| counts_by_year[0].cited_by_count | 1 |
| counts_by_year[1].year | 2024 |
| counts_by_year[1].cited_by_count | 2 |
| counts_by_year[2].year | 2023 |
| counts_by_year[2].cited_by_count | 4 |
| counts_by_year[3].year | 2022 |
| counts_by_year[3].cited_by_count | 7 |
| counts_by_year[4].year | 2021 |
| counts_by_year[4].cited_by_count | 4 |
| locations_count | 3 |
| best_oa_location.id | pmh:oai:re.public.polimi.it:11311/1150440 |
| best_oa_location.is_oa | True |
| best_oa_location.source.id | https://openalex.org/S4306400312 |
| best_oa_location.source.issn | |
| best_oa_location.source.type | repository |
| best_oa_location.source.is_oa | False |
| best_oa_location.source.issn_l | |
| best_oa_location.source.is_core | False |
| best_oa_location.source.is_in_doaj | False |
| best_oa_location.source.display_name | Virtual Community of Pathological Anatomy (University of Castilla La Mancha) |
| best_oa_location.source.host_organization | https://openalex.org/I79189158 |
| best_oa_location.source.host_organization_name | University of Castilla-La Mancha |
| best_oa_location.source.host_organization_lineage | https://openalex.org/I79189158 |
| best_oa_location.license | other-oa |
| best_oa_location.pdf_url | |
| best_oa_location.version | submittedVersion |
| best_oa_location.raw_type | info:eu-repo/semantics/conferenceObject |
| best_oa_location.license_id | https://openalex.org/licenses/other-oa |
| best_oa_location.is_accepted | False |
| best_oa_location.is_published | False |
| best_oa_location.raw_source_name | |
| best_oa_location.landing_page_url | http://hdl.handle.net/11311/1150440 |
| primary_location.id | doi:10.1109/dtis48698.2020.9080961 |
| primary_location.is_oa | False |
| primary_location.source | |
| primary_location.license | |
| primary_location.pdf_url | |
| primary_location.version | publishedVersion |
| primary_location.raw_type | proceedings-article |
| primary_location.license_id | |
| primary_location.is_accepted | True |
| primary_location.is_published | True |
| primary_location.raw_source_name | 2020 15th Design & Technology of Integrated Systems in Nanoscale Era (DTIS) |
| primary_location.landing_page_url | https://doi.org/10.1109/dtis48698.2020.9080961 |
| publication_date | 2020-04-01 |
| publication_year | 2020 |
| referenced_works | https://openalex.org/W2956501515, https://openalex.org/W6603123321, https://openalex.org/W2056140283, https://openalex.org/W2125730340, https://openalex.org/W2029675347, https://openalex.org/W2781893022, https://openalex.org/W2207233201, https://openalex.org/W2785515374, https://openalex.org/W2091750459, https://openalex.org/W1972647831, https://openalex.org/W2783111680, https://openalex.org/W2614714000, https://openalex.org/W2131913992, https://openalex.org/W1605172130, https://openalex.org/W2963255460, https://openalex.org/W2099101940, https://openalex.org/W1992787530, https://openalex.org/W6683630750, https://openalex.org/W4247267706, https://openalex.org/W2056189911, https://openalex.org/W2945055895, https://openalex.org/W2581963379, https://openalex.org/W2005865633, https://openalex.org/W1964330980, https://openalex.org/W2005841208, https://openalex.org/W2123845384, https://openalex.org/W2807535087, https://openalex.org/W2115394282, https://openalex.org/W2404498131, https://openalex.org/W2161998562, https://openalex.org/W76123274, https://openalex.org/W4290629758, https://openalex.org/W4244124617 |
| referenced_works_count | 33 |
| abstract_inverted_index.a | 42, 53, 68, 118, 132, 138, 147, 173, 184 |
| abstract_inverted_index.We | 126, 171 |
| abstract_inverted_index.an | 143 |
| abstract_inverted_index.at | 74 |
| abstract_inverted_index.be | 156 |
| abstract_inverted_index.in | 10, 16, 67, 102, 108 |
| abstract_inverted_index.no | 193 |
| abstract_inverted_index.of | 86, 95, 123, 149, 163 |
| abstract_inverted_index.on | 78, 92, 137, 142 |
| abstract_inverted_index.or | 29 |
| abstract_inverted_index.to | 24, 30, 57, 131, 155, 158, 181 |
| abstract_inverted_index.up | 180 |
| abstract_inverted_index.99% | 162 |
| abstract_inverted_index.BFs | 112 |
| abstract_inverted_index.CPU | 63 |
| abstract_inverted_index.Our | 89, 152 |
| abstract_inverted_index.The | 71 |
| abstract_inverted_index.and | 48, 64, 83, 106, 117, 145, 183, 189, 191 |
| abstract_inverted_index.are | 39, 100 |
| abstract_inverted_index.may | 20 |
| abstract_inverted_index.own | 27 |
| abstract_inverted_index.run | 25 |
| abstract_inverted_index.set | 148 |
| abstract_inverted_index.the | 35, 59, 62, 65, 76, 81, 87, 93, 109, 128 |
| abstract_inverted_index.use | 94 |
| abstract_inverted_index.(and | 120 |
| abstract_inverted_index.CPUs | 12 |
| abstract_inverted_index.FPGA | 144 |
| abstract_inverted_index.HWTs | 38, 79, 165 |
| abstract_inverted_index.Such | 18 |
| abstract_inverted_index.This | 50 |
| abstract_inverted_index.able | 157 |
| abstract_inverted_index.aims | 73 |
| abstract_inverted_index.and, | 13 |
| abstract_inverted_index.been | 7 |
| abstract_inverted_index.both | 45 |
| abstract_inverted_index.case | 133 |
| abstract_inverted_index.data | 84 |
| abstract_inverted_index.from | 46, 178 |
| abstract_inverted_index.gain | 31 |
| abstract_inverted_index.have | 6 |
| abstract_inverted_index.more | 160 |
| abstract_inverted_index.over | 34 |
| abstract_inverted_index.than | 161 |
| abstract_inverted_index.that | 99 |
| abstract_inverted_index.very | 14 |
| abstract_inverted_index.with | 167, 192 |
| abstract_inverted_index.zero | 114, 168 |
| abstract_inverted_index.(BFs) | 98 |
| abstract_inverted_index.0.68% | 179, 188 |
| abstract_inverted_index.Bloom | 96 |
| abstract_inverted_index.allow | 21 |
| abstract_inverted_index.based | 136 |
| abstract_inverted_index.false | 115, 169 |
| abstract_inverted_index.meant | 56 |
| abstract_inverted_index.paper | 51 |
| abstract_inverted_index.small | 119 |
| abstract_inverted_index.study | 134 |
| abstract_inverted_index.table | 175 |
| abstract_inverted_index.their | 26 |
| abstract_inverted_index.users | 23 |
| abstract_inverted_index.(HWTs) | 5 |
| abstract_inverted_index.0.99%, | 190 |
| abstract_inverted_index.10.52% | 182 |
| abstract_inverted_index.Horses | 4 |
| abstract_inverted_index.RISC-V | 139 |
| abstract_inverted_index.Trojan | 3 |
| abstract_inverted_index.ad-hoc | 103 |
| abstract_inverted_index.alarms | 116 |
| abstract_inverted_index.detect | 159 |
| abstract_inverted_index.lookup | 174 |
| abstract_inverted_index.memory | 66 |
| abstract_inverted_index.relies | 91 |
| abstract_inverted_index.shield | 58 |
| abstract_inverted_index.system | 135 |
| abstract_inverted_index.threat | 44 |
| abstract_inverted_index.Filters | 97 |
| abstract_inverted_index.Hip-Hop | 185 |
| abstract_inverted_index.academy | 47 |
| abstract_inverted_index.alarms. | 125, 170 |
| abstract_inverted_index.applied | 127 |
| abstract_inverted_index.attacks | 19 |
| abstract_inverted_index.between | 61, 187 |
| abstract_inverted_index.ranging | 177 |
| abstract_inverted_index.running | 146 |
| abstract_inverted_index.serious | 43 |
| abstract_inverted_index.system. | 36, 70, 88 |
| abstract_inverted_index.working | 194 |
| abstract_inverted_index.Hardware | 2 |
| abstract_inverted_index.Software | 0 |
| abstract_inverted_index.checkers | 105 |
| abstract_inverted_index.designed | 104 |
| abstract_inverted_index.included | 101 |
| abstract_inverted_index.inserted | 9 |
| abstract_inverted_index.measured | 172 |
| abstract_inverted_index.memories | 85 |
| abstract_inverted_index.nowadays | 40 |
| abstract_inverted_index.overhead | 176, 186 |
| abstract_inverted_index.possible | 164 |
| abstract_inverted_index.presents | 52 |
| abstract_inverted_index.proposal | 90, 153 |
| abstract_inverted_index.software | 28, 150 |
| abstract_inverted_index.currently | 8 |
| abstract_inverted_index.detecting | 75 |
| abstract_inverted_index.frequency | 195 |
| abstract_inverted_index.guarantee | 113 |
| abstract_inverted_index.industry. | 49 |
| abstract_inverted_index.infesting | 80 |
| abstract_inverted_index.malicious | 22 |
| abstract_inverted_index.memories. | 17 |
| abstract_inverted_index.recently, | 15 |
| abstract_inverted_index.Therefore, | 37 |
| abstract_inverted_index.activation | 77 |
| abstract_inverted_index.commercial | 11 |
| abstract_inverted_index.considered | 41 |
| abstract_inverted_index.integrated | 107 |
| abstract_inverted_index.percentage | 122 |
| abstract_inverted_index.privileges | 33 |
| abstract_inverted_index.protection | 54, 110, 129 |
| abstract_inverted_index.reduction. | 196 |
| abstract_inverted_index.undetected | 124 |
| abstract_inverted_index.activations | 166 |
| abstract_inverted_index.benchmarks. | 151 |
| abstract_inverted_index.exploitable | 1 |
| abstract_inverted_index.implemented | 141 |
| abstract_inverted_index.instruction | 82 |
| abstract_inverted_index.architecture | 55, 72, 130 |
| abstract_inverted_index.demonstrated | 154 |
| abstract_inverted_index.unauthorized | 32 |
| abstract_inverted_index.architecture. | 111 |
| abstract_inverted_index.communication | 60 |
| abstract_inverted_index.configurable) | 121 |
| abstract_inverted_index.microprocessor | 140 |
| abstract_inverted_index.microprocessor-based | 69 |
| cited_by_percentile_year.max | 99 |
| cited_by_percentile_year.min | 91 |
| countries_distinct_count | 3 |
| institutions_distinct_count | 5 |
| sustainable_development_goals[0].id | https://metadata.un.org/sdg/9 |
| sustainable_development_goals[0].score | 0.6100000143051147 |
| sustainable_development_goals[0].display_name | Industry, innovation and infrastructure |
| citation_normalized_percentile.value | 0.93295615 |
| citation_normalized_percentile.is_in_top_1_percent | False |
| citation_normalized_percentile.is_in_top_10_percent | True |