A reconfigurable heterogeneous in-memory computing architecture for variable precision computation: a software-hardware co-design approach Article Swipe

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Yen-Yu Chen , Hanjie Liu , Siqi Wang , J.-X. Mi , Xiong Xing , Yuexi Lv , Aifei Zhang , Lichuan Luo , Yong Pei , Minghua Tang , Wang Kang ·

YOU? · · 2025 · Open Access · · DOI: https://doi.org/10.1007/s44275-025-00028-1

In-memory computing (IMC) has emerged as a promising approach for accelerating deep neural network (DNN) inference by relocating computations to memory arrays. However, the efficacy of analog IMC diminishes when higher computational precision is required due to inherent device non-idealities. In this paper, we present a reconfigurable heterogeneous architecture that integrates a digital computing unit (DCU) with an analog IMC unit (AIMCU). The computational data is partitioned into most significant bits (MSBs) and least significant bits (LSBs); the sparse MSBs are processed by the DCU with lossless precision, and the dense LSBs are computed by the AIMCU for high energy efficiency, thereby enhancing inference accuracy and optimizing area efficiency. The architecture also features multiple modes that support variable-precision input splitting and weight splitting computation. Additionally, by leveraging hardware characteristics, we have developed several optimization strategies for neural network deployment, including parameter splitting, shifting algorithms, and sparse weight mapping. The experimental results show that the perceptual evaluation of speech quality (PESQ) of the deep complex convolution recurrent network (DCCRN) improved by 28.98%, while the peak signal-to-noise ratio (PSNR) of the super-resolution network (SRN) increased by 17.27%. Compared to previous state-of-the-art (SOTA) work, the reconfigurable heterogeneous-IMC-based system on a chip (SoC) demonstrates a significant improvement in energy efficiency while achieving accuracy close to that of pure digital computing.

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Field-Programmable Gate Array

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Computer science Computer architecture Computation Hardware architecture Variable (mathematics) Architecture Parallel computing Software Reconfigurable computing Embedded system Computer hardware Field-programmable gate array Operating system Algorithm Mathematics Art Visual arts Mathematical analysis

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Type: article
Language: en
Landing Page: https://doi.org/10.1007/s44275-025-00028-1
PDF: https://link.springer.com/content/pdf/10.1007/s44275-025-00028-1.pdf
OA Status: hybrid
References: 26
Related Works: 10
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DOI: https://doi.org/10.1007/s44275-025-00028-1

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Title: A reconfigurable heterogeneous in-memory computing architecture for variable precision computation: a software-hardware co-design approach

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Language: en

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Publication year: 2025

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Publication date: 2025-07-14

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Authors: Yen-Yu Chen, Hanjie Liu, Siqi Wang, J.-X. Mi, Xiong Xing, Yuexi Lv, Aifei Zhang, Lichuan Luo, Yong Pei, Minghua Tang, Wang Kang

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Landing page: https://doi.org/10.1007/s44275-025-00028-1

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PDF URL: https://link.springer.com/content/pdf/10.1007/s44275-025-00028-1.pdf

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Concepts: Computer science, Computer architecture, Computation, Hardware architecture, Variable (mathematics), Architecture, Parallel computing, Software, Reconfigurable computing, Embedded system, Computer hardware, Field-programmable gate array, Operating system, Algorithm, Mathematics, Art, Visual arts, Mathematical analysis

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