An unprotected RISC-V Soft-core processor on an SRAM FPGA: Is it as bad as it sounds? Article Swipe
Bruno Endres Forlin
,
Wouter van Huffelen
,
Carlo Cazzaniga
,
Paolo Rech
,
Nikolaos Alachiotis
,
Marco Ottavi
·
YOU?
·
· 2023
· Open Access
·
· DOI: https://doi.org/10.1109/ets56758.2023.10174076
YOU?
·
· 2023
· Open Access
·
· DOI: https://doi.org/10.1109/ets56758.2023.10174076
Fast development, low cost, and reconfigurability are becoming critical factors for aerospace applications, making SRAM FPGAs attractive. However, SRAM FPGAs are prone to errors in the user and on the configuration bits. For their correct functioning, they must be capable of withstanding failures without sacrificing much performance. When adjusting a soft core for these applications, it is essential to know where redundancies are necessary, to avoid unnecessary overhead. We characterize the reliability of an unprotected RISC-V microcontroller using an accelerated neutron beam. Our investigation shows that, for our chosen benchmark and processor, the user data in the memory banks is the leading cause of the total number of errors in the application. By reversing the benchmark operations, we could root cause the origin of the observed errors and found that most of the data corruption detected during the runs stem from previously corrupt input data or from output data that were corrupted while transmitting.
Related Topics
Concepts
Static random-access memory
Computer science
Reconfigurability
Embedded system
Benchmark (surveying)
Field-programmable gate array
Multi-core processor
Overhead (engineering)
Microcontroller
Reliability (semiconductor)
Computer hardware
Parallel computing
Operating system
Power (physics)
Geography
Quantum mechanics
Geodesy
Physics
Metadata
- Type
- article
- Language
- en
- Landing Page
- https://doi.org/10.1109/ets56758.2023.10174076
- OA Status
- gold
- Cited By
- 3
- References
- 20
- Related Works
- 10
- OpenAlex ID
- https://openalex.org/W4384009476
All OpenAlex metadata
Raw OpenAlex JSON
- OpenAlex ID
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https://openalex.org/W4384009476Canonical identifier for this work in OpenAlex
- DOI
-
https://doi.org/10.1109/ets56758.2023.10174076Digital Object Identifier
- Title
-
An unprotected RISC-V Soft-core processor on an SRAM FPGA: Is it as bad as it sounds?Work title
- Type
-
articleOpenAlex work type
- Language
-
enPrimary language
- Publication year
-
2023Year of publication
- Publication date
-
2023-05-22Full publication date if available
- Authors
-
Bruno Endres Forlin, Wouter van Huffelen, Carlo Cazzaniga, Paolo Rech, Nikolaos Alachiotis, Marco OttaviList of authors in order
- Landing page
-
https://doi.org/10.1109/ets56758.2023.10174076Publisher landing page
- Open access
-
YesWhether a free full text is available
- OA status
-
goldOpen access status per OpenAlex
- OA URL
-
https://research.utwente.nl/en/publications/021d716d-f5e8-470b-9733-290911607378Direct OA link when available
- Concepts
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Static random-access memory, Computer science, Reconfigurability, Embedded system, Benchmark (surveying), Field-programmable gate array, Multi-core processor, Overhead (engineering), Microcontroller, Reliability (semiconductor), Computer hardware, Parallel computing, Operating system, Power (physics), Geography, Quantum mechanics, Geodesy, PhysicsTop concepts (fields/topics) attached by OpenAlex
- Cited by
-
3Total citation count in OpenAlex
- Citations by year (recent)
-
2025: 2, 2024: 1Per-year citation counts (last 5 years)
- References (count)
-
20Number of works referenced by this work
- Related works (count)
-
10Other works algorithmically related by OpenAlex
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