Barrier-Free Large-Scale Sparse Tensor Accelerator (BARISTA) For\n Convolutional Neural Networks Article Swipe

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Ashish Gondimalla , Sree Charan Gundabolu , T. N. Vijaykumar , Mithuna Thottethodi · YOU? · · 2021 · Open Access · · DOI: https://doi.org/10.48550/arxiv.2104.08734

Convolutional neural networks (CNNs) are emerging as powerful tools for\nvisual recognition. Recent architecture proposals for sparse CNNs exploit zeros\nin the feature maps and filters for performance and energy without losing\naccuracy. Sparse architectures that exploit two-sided sparsity in both feature\nmaps and filters have been studied only at small scales (e.g., 1K\nmultiply-accumulate(MAC) units). However, to realize their advantages in full,\nthe sparse architectures have to be scaled up to levels of the dense\narchitectures (e.g., 32K MACs in the TPU). Such scaling is challenging since\nachieving reuse through broadcasts incurs implicit barrier cost raises the\ninter-related issues of load imbalance, buffering, and on-chip bandwidth\ndemand. SparTen, a previous scheme, addresses one aspect of load balancing but\nnot other aspects, nor the other issues of buffering and bandwidth. To that\nend, we propose the barrier-free large-scale sparse tensor accelerator\n(BARISTA). BARISTA (1) is the first architecture for scaling up sparse CNN\naccelerators; (2) reduces on-chip bandwidth demand by telescoping\nrequest-combining the input map requests and snarfing the filter requests; (3)\nreduces buffering via basic buffer sharing and avoids the ensuing barriers\nbetween consecutive input maps by coloring the output buffers; (4) load\nbalances intra-filter work via dynamic round-robin work assignment; and (5)\nemploys hierarchical buffering which achieves high cache bandwidth via a few,\nwide, shared buffers and low buffering via narrower, private buffers at the\ncompute. Our simulations show that, on average, barista performs 5.4x, 2.2x,\n1.7x, 2.5x better than a dense, a one-sided, a naively-scaled two-sided, and an\niso-area two-sided architecture, respectively. Using 45-nm technology, ASIC\nsynthesis of our RTL design for four clusters of 8K MACs at 1 GHz clock speed,\nreports 213 mm$^2$ area and 170 W power.\n

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preprint

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http://arxiv.org/abs/2104.08734

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https://doi.org/10.48550/arxiv.2104.08734

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Barrier-Free Large-Scale Sparse Tensor Accelerator (BARISTA) For\n Convolutional Neural Networks

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preprint

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2021

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2021-04-18

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Ashish Gondimalla, Sree Charan Gundabolu, T. N. Vijaykumar, Mithuna Thottethodi

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https://arxiv.org/abs/2104.08734

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Computer science, Convolutional neural network, Exploit, Bandwidth (computing), Parallel computing, Cache, Scaling, Computer engineering, Memory bandwidth, Reuse, Artificial intelligence, Computer network, Geometry, Computer security, Mathematics, Ecology, Biology

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