Building Complete Heterogeneous Systems-on-Chip in C: From Hardware Accelerators to CPUs Article Swipe
Qilin Si
,
Santosh Shetty
,
Benjamin Carrión Schäfer
·
YOU?
·
· 2021
· Open Access
·
· DOI: https://doi.org/10.3390/electronics10141746
YOU?
·
· 2021
· Open Access
·
· DOI: https://doi.org/10.3390/electronics10141746
High-Level Synthesis (HLS) dramatically accelerates the design and verification of individual components within larger VLSI systems. With most complex Integrated Circuits (ICs) being now heterogeneous Systems-on-Chip (SoCs), HLS has been traditionally used to design the dedicated hardware accelerators such as encryption cores and Digital Signal Processing (DSP) image processing accelerators. Unfortunately, HLS is a single process (component) synthesis method. Thus, the integration of these accelerators has to be performed at the RT level (Verilog or VHDL). This implies that the system-level verification needs to be performed at lower levels of abstraction, which significantly diminishes the benefits of using HLS. To address this, this work presents a methodology to generate entire heterogeneous SoCs in C. This work introduces two main contributions that enable this: first, an automatic bus generator that generates a synthesizable behavioral description of standard on-chip buses and, second, a library of synthesizable bus interfaces that allow any component in the system to send or receive data through the bus. Moreover, this work investigates the generation of processors and interfaces (peripherals) at the behavioral level as these are important parts of any SoCs, but have long been thought not to be efficiently synthesizable using HLS. Generating complete SoCs in C has significant advantages over traditional approaches. First, it enables the generation of fast cycle-accurate simulation models of the entire SoC, making the verification faster and easier. Second, it allows completely isolating the bus implementation details from the developers’ view, allowing the change between bus protocols with only minor changes in the designers’ code. Thirdly, it allows generating different SoC variants quickly by only changing the HLS synthesis options. Experimental results highlight these benefits.
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Metadata
- Type
- article
- Language
- en
- Landing Page
- https://doi.org/10.3390/electronics10141746
- https://www.mdpi.com/2079-9292/10/14/1746/pdf?version=1626923728
- OA Status
- gold
- Cited By
- 4
- References
- 28
- Related Works
- 10
- OpenAlex ID
- https://openalex.org/W3184942322
All OpenAlex metadata
Raw OpenAlex JSON
- OpenAlex ID
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https://openalex.org/W3184942322Canonical identifier for this work in OpenAlex
- DOI
-
https://doi.org/10.3390/electronics10141746Digital Object Identifier
- Title
-
Building Complete Heterogeneous Systems-on-Chip in C: From Hardware Accelerators to CPUsWork title
- Type
-
articleOpenAlex work type
- Language
-
enPrimary language
- Publication year
-
2021Year of publication
- Publication date
-
2021-07-20Full publication date if available
- Authors
-
Qilin Si, Santosh Shetty, Benjamin Carrión SchäferList of authors in order
- Landing page
-
https://doi.org/10.3390/electronics10141746Publisher landing page
- PDF URL
-
https://www.mdpi.com/2079-9292/10/14/1746/pdf?version=1626923728Direct link to full text PDF
- Open access
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YesWhether a free full text is available
- OA status
-
goldOpen access status per OpenAlex
- OA URL
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https://www.mdpi.com/2079-9292/10/14/1746/pdf?version=1626923728Direct OA link when available
- Concepts
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Embedded system, Computer science, VHDL, Verilog, System on a chip, High-level synthesis, Computer hardware, Process (computing), Computer architecture, Field-programmable gate array, Operating systemTop concepts (fields/topics) attached by OpenAlex
- Cited by
-
4Total citation count in OpenAlex
- Citations by year (recent)
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2024: 1, 2023: 1, 2022: 1, 2021: 1Per-year citation counts (last 5 years)
- References (count)
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28Number of works referenced by this work
- Related works (count)
-
10Other works algorithmically related by OpenAlex
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| referenced_works_count | 28 |
| abstract_inverted_index.C | 200 |
| abstract_inverted_index.a | 53, 105, 130, 140 |
| abstract_inverted_index.C. | 113 |
| abstract_inverted_index.RT | 71 |
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| abstract_inverted_index.as | 39, 176 |
| abstract_inverted_index.at | 69, 86, 172 |
| abstract_inverted_index.be | 67, 84, 191 |
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| abstract_inverted_index.to | 32, 66, 83, 107, 153, 190 |
| abstract_inverted_index.HLS | 27, 51, 266 |
| abstract_inverted_index.SoC | 259 |
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| abstract_inverted_index.Thus, | 59 |
| abstract_inverted_index.allow | 147 |
| abstract_inverted_index.being | 22 |
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| corresponding_author_ids | https://openalex.org/A5064356970 |
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| corresponding_institution_ids | https://openalex.org/I162577319 |
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| citation_normalized_percentile.is_in_top_10_percent | False |