Circuit Representation Learning with Masked Gate Modeling and Verilog-AIG Alignment Article Swipe
Haoyuan Wu
,
Han Zheng
,
Yuan Pu
,
Bei Yu
·
YOU?
·
· 2025
· Open Access
·
· DOI: https://doi.org/10.48550/arxiv.2502.12732
YOU?
·
· 2025
· Open Access
·
· DOI: https://doi.org/10.48550/arxiv.2502.12732
Understanding the structure and function of circuits is crucial for electronic design automation (EDA). Circuits can be formulated as And-Inverter graphs (AIGs), enabling efficient implementation of representation learning through graph neural networks (GNNs). Masked modeling paradigms have been proven effective in graph representation learning. However, masking augmentation to original circuits will destroy their logical equivalence, which is unsuitable for circuit representation learning. Moreover, existing masked modeling paradigms often prioritize structural information at the expense of abstract information such as circuit function. To address these limitations, we introduce MGVGA, a novel constrained masked modeling paradigm incorporating masked gate modeling (MGM) and Verilog-AIG alignment (VGA). Specifically, MGM preserves logical equivalence by masking gates in the latent space rather than in the original circuits, subsequently reconstructing the attributes of these masked gates. Meanwhile, large language models (LLMs) have demonstrated an excellent understanding of the Verilog code functionality. Building upon this capability, VGA performs masking operations on original circuits and reconstructs masked gates under the constraints of equivalent Verilog codes, enabling GNNs to learn circuit functions from LLMs. We evaluate MGVGA on various logic synthesis tasks for EDA and show the superior performance of MGVGA compared to previous state-of-the-art methods. Our code is available at https://github.com/wuhy68/MGVGA.
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Metadata
- Type
- preprint
- Language
- en
- Landing Page
- http://arxiv.org/abs/2502.12732
- https://arxiv.org/pdf/2502.12732
- OA Status
- green
- Related Works
- 10
- OpenAlex ID
- https://openalex.org/W4407759737
All OpenAlex metadata
Raw OpenAlex JSON
- OpenAlex ID
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https://openalex.org/W4407759737Canonical identifier for this work in OpenAlex
- DOI
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https://doi.org/10.48550/arxiv.2502.12732Digital Object Identifier
- Title
-
Circuit Representation Learning with Masked Gate Modeling and Verilog-AIG AlignmentWork title
- Type
-
preprintOpenAlex work type
- Language
-
enPrimary language
- Publication year
-
2025Year of publication
- Publication date
-
2025-02-18Full publication date if available
- Authors
-
Haoyuan Wu, Han Zheng, Yuan Pu, Bei YuList of authors in order
- Landing page
-
https://arxiv.org/abs/2502.12732Publisher landing page
- PDF URL
-
https://arxiv.org/pdf/2502.12732Direct link to full text PDF
- Open access
-
YesWhether a free full text is available
- OA status
-
greenOpen access status per OpenAlex
- OA URL
-
https://arxiv.org/pdf/2502.12732Direct OA link when available
- Concepts
-
Representation (politics), Computer science, Verilog, Computer hardware, Political science, Field-programmable gate array, Politics, LawTop concepts (fields/topics) attached by OpenAlex
- Cited by
-
0Total citation count in OpenAlex
- Related works (count)
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10Other works algorithmically related by OpenAlex
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