Cohet: A CXL-Driven Coherent Heterogeneous Computing Framework with Hardware-Calibrated Full-System Simulation Article Swipe
Wang, Yanjing
,
Wu Lizhou
,
Gao, Sunfeng
,
Tang Yibo
,
Luo Jun-hui
,
Wang Zicong
,
Ou Yang
,
Dong, Dezun
,
Xiao Nong
,
Lai Mingche
·
YOU?
·
· 2025
· Open Access
·
YOU?
·
· 2025
· Open Access
·
Conventional heterogeneous computing systems built on PCIe interconnects suffer from inefficient fine-grained host-device interactions and complex programming models. In recent years, many proprietary and open cache-coherent interconnect standards have emerged, among which compute express link (CXL) prevails in the open-standard domain after acquiring several competing solutions. Although CXL-based coherent heterogeneous computing holds the potential to fundamentally transform the collaborative computing mode of CPUs and XPUs, research in this direction remains hampered by the scarcity of available CXL-supported platforms, immature software/hardware ecosystems, and unclear application prospects. This paper presents Cohet, the first CXL-driven coherent heterogeneous computing framework. Cohet decouples the compute and memory resources to form unbiased CPU and XPU pools which share a single unified and coherent memory pool. It exposes a standard malloc/mmap interface to both CPU and XPU compute threads, leaving the OS dealing with smart memory allocation and management of heterogeneous resources. To facilitate Cohet research, we also present a full-system cycle-level simulator named SimCXL, which is capable of modeling all CXL sub-protocols and device types. SimCXL has been rigorously calibrated against a real CXL testbed with various CXL memory and accelerators, showing an average simulation error of 3%. Our evaluation reveals that CXL.cache reduces latency by 68% and increases bandwidth by 14.4x compared to DMA transfers at cacheline granularity. Building upon these insights, we demonstrate the benefits of Cohet with two killer apps, which are remote atomic operation (RAO) and remote procedure call (RPC). Compared to PCIe-NIC design, CXL-NIC achieves a 5.5 to 40.2x speedup for RAO offloading and an average speedup of 1.86x for RPC (de)serialization offloading.
Related Topics
Concepts
Computer science
Speedup
Testbed
PCI Express
Symmetric multiprocessor system
Parallel computing
Distributed computing
Latency (audio)
Direct memory access
Exascale computing
Central processing unit
Supercomputer
Unconventional computing
Heterogeneous network
Domain (mathematical analysis)
Interface (matter)
Shared memory
In-Memory Processing
Bandwidth (computing)
Computer engineering
Proxy (statistics)
Computational science
Network interface
Low latency (capital markets)
Computer architecture
Programming paradigm
Memory bandwidth
Multi-core processor
Remote direct memory access
Many core
Key (lock)
Application programming interface
Integer programming
High memory
Metadata
- Type
- article
- Landing Page
- http://arxiv.org/abs/2511.23011
- https://arxiv.org/pdf/2511.23011
- OA Status
- green
- OpenAlex ID
- https://openalex.org/W7108247240
All OpenAlex metadata
Raw OpenAlex JSON
- OpenAlex ID
-
https://openalex.org/W7108247240Canonical identifier for this work in OpenAlex
- Title
-
Cohet: A CXL-Driven Coherent Heterogeneous Computing Framework with Hardware-Calibrated Full-System SimulationWork title
- Type
-
articleOpenAlex work type
- Publication year
-
2025Year of publication
- Publication date
-
2025-11-28Full publication date if available
- Authors
-
Wang, Yanjing, Wu Lizhou, Gao, Sunfeng, Tang Yibo, Luo Jun-hui, Wang Zicong, Ou Yang, Dong, Dezun, Xiao Nong, Lai MingcheList of authors in order
- Landing page
-
https://arxiv.org/abs/2511.23011Publisher landing page
- PDF URL
-
https://arxiv.org/pdf/2511.23011Direct link to full text PDF
- Open access
-
YesWhether a free full text is available
- OA status
-
greenOpen access status per OpenAlex
- OA URL
-
https://arxiv.org/pdf/2511.23011Direct OA link when available
- Concepts
-
Computer science, Speedup, Testbed, PCI Express, Symmetric multiprocessor system, Parallel computing, Distributed computing, Latency (audio), Direct memory access, Exascale computing, Central processing unit, Supercomputer, Unconventional computing, Heterogeneous network, Domain (mathematical analysis), Interface (matter), Shared memory, In-Memory Processing, Bandwidth (computing), Computer engineering, Proxy (statistics), Computational science, Network interface, Low latency (capital markets), Computer architecture, Programming paradigm, Memory bandwidth, Multi-core processor, Remote direct memory access, Many core, Key (lock), Application programming interface, Integer programming, High memoryTop concepts (fields/topics) attached by OpenAlex
- Cited by
-
0Total citation count in OpenAlex
Full payload
| id | https://openalex.org/W7108247240 |
|---|---|
| doi | |
| ids.openalex | https://openalex.org/W7108247240 |
| fwci | 0.0 |
| type | article |
| title | Cohet: A CXL-Driven Coherent Heterogeneous Computing Framework with Hardware-Calibrated Full-System Simulation |
| biblio.issue | |
| biblio.volume | |
| biblio.last_page | |
| biblio.first_page | |
| topics[0].id | https://openalex.org/T10054 |
| topics[0].field.id | https://openalex.org/fields/17 |
| topics[0].field.display_name | Computer Science |
| topics[0].score | 0.6027531027793884 |
| topics[0].domain.id | https://openalex.org/domains/3 |
| topics[0].domain.display_name | Physical Sciences |
| topics[0].subfield.id | https://openalex.org/subfields/1708 |
| topics[0].subfield.display_name | Hardware and Architecture |
| topics[0].display_name | Parallel Computing and Optimization Techniques |
| topics[1].id | https://openalex.org/T11181 |
| topics[1].field.id | https://openalex.org/fields/17 |
| topics[1].field.display_name | Computer Science |
| topics[1].score | 0.1700003743171692 |
| topics[1].domain.id | https://openalex.org/domains/3 |
| topics[1].domain.display_name | Physical Sciences |
| topics[1].subfield.id | https://openalex.org/subfields/1705 |
| topics[1].subfield.display_name | Computer Networks and Communications |
| topics[1].display_name | Advanced Data Storage Technologies |
| topics[2].id | https://openalex.org/T10101 |
| topics[2].field.id | https://openalex.org/fields/17 |
| topics[2].field.display_name | Computer Science |
| topics[2].score | 0.1030462458729744 |
| topics[2].domain.id | https://openalex.org/domains/3 |
| topics[2].domain.display_name | Physical Sciences |
| topics[2].subfield.id | https://openalex.org/subfields/1710 |
| topics[2].subfield.display_name | Information Systems |
| topics[2].display_name | Cloud Computing and Resource Management |
| is_xpac | False |
| apc_list | |
| apc_paid | |
| concepts[0].id | https://openalex.org/C41008148 |
| concepts[0].level | 0 |
| concepts[0].score | 0.8320962190628052 |
| concepts[0].wikidata | https://www.wikidata.org/wiki/Q21198 |
| concepts[0].display_name | Computer science |
| concepts[1].id | https://openalex.org/C68339613 |
| concepts[1].level | 2 |
| concepts[1].score | 0.8200057148933411 |
| concepts[1].wikidata | https://www.wikidata.org/wiki/Q1549489 |
| concepts[1].display_name | Speedup |
| concepts[2].id | https://openalex.org/C31395832 |
| concepts[2].level | 2 |
| concepts[2].score | 0.780371367931366 |
| concepts[2].wikidata | https://www.wikidata.org/wiki/Q1318674 |
| concepts[2].display_name | Testbed |
| concepts[3].id | https://openalex.org/C64270927 |
| concepts[3].level | 3 |
| concepts[3].score | 0.730304479598999 |
| concepts[3].wikidata | https://www.wikidata.org/wiki/Q206924 |
| concepts[3].display_name | PCI Express |
| concepts[4].id | https://openalex.org/C172430144 |
| concepts[4].level | 2 |
| concepts[4].score | 0.6677523851394653 |
| concepts[4].wikidata | https://www.wikidata.org/wiki/Q17111997 |
| concepts[4].display_name | Symmetric multiprocessor system |
| concepts[5].id | https://openalex.org/C173608175 |
| concepts[5].level | 1 |
| concepts[5].score | 0.521955132484436 |
| concepts[5].wikidata | https://www.wikidata.org/wiki/Q232661 |
| concepts[5].display_name | Parallel computing |
| concepts[6].id | https://openalex.org/C120314980 |
| concepts[6].level | 1 |
| concepts[6].score | 0.4964469075202942 |
| concepts[6].wikidata | https://www.wikidata.org/wiki/Q180634 |
| concepts[6].display_name | Distributed computing |
| concepts[7].id | https://openalex.org/C82876162 |
| concepts[7].level | 2 |
| concepts[7].score | 0.4431924521923065 |
| concepts[7].wikidata | https://www.wikidata.org/wiki/Q17096504 |
| concepts[7].display_name | Latency (audio) |
| concepts[8].id | https://openalex.org/C37724790 |
| concepts[8].level | 3 |
| concepts[8].score | 0.40952882170677185 |
| concepts[8].wikidata | https://www.wikidata.org/wiki/Q210813 |
| concepts[8].display_name | Direct memory access |
| concepts[9].id | https://openalex.org/C2778837361 |
| concepts[9].level | 3 |
| concepts[9].score | 0.3911478817462921 |
| concepts[9].wikidata | https://www.wikidata.org/wiki/Q2450880 |
| concepts[9].display_name | Exascale computing |
| concepts[10].id | https://openalex.org/C49154492 |
| concepts[10].level | 2 |
| concepts[10].score | 0.38133496046066284 |
| concepts[10].wikidata | https://www.wikidata.org/wiki/Q5300 |
| concepts[10].display_name | Central processing unit |
| concepts[11].id | https://openalex.org/C83283714 |
| concepts[11].level | 2 |
| concepts[11].score | 0.3804810643196106 |
| concepts[11].wikidata | https://www.wikidata.org/wiki/Q121117 |
| concepts[11].display_name | Supercomputer |
| concepts[12].id | https://openalex.org/C23375383 |
| concepts[12].level | 2 |
| concepts[12].score | 0.3638259172439575 |
| concepts[12].wikidata | https://www.wikidata.org/wiki/Q176499 |
| concepts[12].display_name | Unconventional computing |
| concepts[13].id | https://openalex.org/C158207573 |
| concepts[13].level | 4 |
| concepts[13].score | 0.36170336604118347 |
| concepts[13].wikidata | https://www.wikidata.org/wiki/Q5747224 |
| concepts[13].display_name | Heterogeneous network |
| concepts[14].id | https://openalex.org/C36503486 |
| concepts[14].level | 2 |
| concepts[14].score | 0.34881219267845154 |
| concepts[14].wikidata | https://www.wikidata.org/wiki/Q11235244 |
| concepts[14].display_name | Domain (mathematical analysis) |
| concepts[15].id | https://openalex.org/C113843644 |
| concepts[15].level | 4 |
| concepts[15].score | 0.34840741753578186 |
| concepts[15].wikidata | https://www.wikidata.org/wiki/Q901882 |
| concepts[15].display_name | Interface (matter) |
| concepts[16].id | https://openalex.org/C133875982 |
| concepts[16].level | 2 |
| concepts[16].score | 0.3431723415851593 |
| concepts[16].wikidata | https://www.wikidata.org/wiki/Q764810 |
| concepts[16].display_name | Shared memory |
| concepts[17].id | https://openalex.org/C123593499 |
| concepts[17].level | 5 |
| concepts[17].score | 0.3312065303325653 |
| concepts[17].wikidata | https://www.wikidata.org/wiki/Q6008583 |
| concepts[17].display_name | In-Memory Processing |
| concepts[18].id | https://openalex.org/C2776257435 |
| concepts[18].level | 2 |
| concepts[18].score | 0.31944888830184937 |
| concepts[18].wikidata | https://www.wikidata.org/wiki/Q1576430 |
| concepts[18].display_name | Bandwidth (computing) |
| concepts[19].id | https://openalex.org/C113775141 |
| concepts[19].level | 1 |
| concepts[19].score | 0.2966407537460327 |
| concepts[19].wikidata | https://www.wikidata.org/wiki/Q428691 |
| concepts[19].display_name | Computer engineering |
| concepts[20].id | https://openalex.org/C2780148112 |
| concepts[20].level | 2 |
| concepts[20].score | 0.29257023334503174 |
| concepts[20].wikidata | https://www.wikidata.org/wiki/Q1432581 |
| concepts[20].display_name | Proxy (statistics) |
| concepts[21].id | https://openalex.org/C459310 |
| concepts[21].level | 1 |
| concepts[21].score | 0.2894091308116913 |
| concepts[21].wikidata | https://www.wikidata.org/wiki/Q117801 |
| concepts[21].display_name | Computational science |
| concepts[22].id | https://openalex.org/C103987645 |
| concepts[22].level | 3 |
| concepts[22].score | 0.2857643961906433 |
| concepts[22].wikidata | https://www.wikidata.org/wiki/Q985806 |
| concepts[22].display_name | Network interface |
| concepts[23].id | https://openalex.org/C46637626 |
| concepts[23].level | 2 |
| concepts[23].score | 0.2856731414794922 |
| concepts[23].wikidata | https://www.wikidata.org/wiki/Q6693015 |
| concepts[23].display_name | Low latency (capital markets) |
| concepts[24].id | https://openalex.org/C118524514 |
| concepts[24].level | 1 |
| concepts[24].score | 0.2779330611228943 |
| concepts[24].wikidata | https://www.wikidata.org/wiki/Q173212 |
| concepts[24].display_name | Computer architecture |
| concepts[25].id | https://openalex.org/C34165917 |
| concepts[25].level | 2 |
| concepts[25].score | 0.26747748255729675 |
| concepts[25].wikidata | https://www.wikidata.org/wiki/Q188267 |
| concepts[25].display_name | Programming paradigm |
| concepts[26].id | https://openalex.org/C188045654 |
| concepts[26].level | 2 |
| concepts[26].score | 0.26699432730674744 |
| concepts[26].wikidata | https://www.wikidata.org/wiki/Q17148339 |
| concepts[26].display_name | Memory bandwidth |
| concepts[27].id | https://openalex.org/C78766204 |
| concepts[27].level | 2 |
| concepts[27].score | 0.2625525891780853 |
| concepts[27].wikidata | https://www.wikidata.org/wiki/Q555032 |
| concepts[27].display_name | Multi-core processor |
| concepts[28].id | https://openalex.org/C130795937 |
| concepts[28].level | 2 |
| concepts[28].score | 0.2596116364002228 |
| concepts[28].wikidata | https://www.wikidata.org/wiki/Q2561570 |
| concepts[28].display_name | Remote direct memory access |
| concepts[29].id | https://openalex.org/C3020431745 |
| concepts[29].level | 2 |
| concepts[29].score | 0.25481465458869934 |
| concepts[29].wikidata | https://www.wikidata.org/wiki/Q25325220 |
| concepts[29].display_name | Many core |
| concepts[30].id | https://openalex.org/C26517878 |
| concepts[30].level | 2 |
| concepts[30].score | 0.2542282044887543 |
| concepts[30].wikidata | https://www.wikidata.org/wiki/Q228039 |
| concepts[30].display_name | Key (lock) |
| concepts[31].id | https://openalex.org/C99613125 |
| concepts[31].level | 2 |
| concepts[31].score | 0.2539231479167938 |
| concepts[31].wikidata | https://www.wikidata.org/wiki/Q165194 |
| concepts[31].display_name | Application programming interface |
| concepts[32].id | https://openalex.org/C56086750 |
| concepts[32].level | 2 |
| concepts[32].score | 0.2523142099380493 |
| concepts[32].wikidata | https://www.wikidata.org/wiki/Q6042592 |
| concepts[32].display_name | Integer programming |
| concepts[33].id | https://openalex.org/C2781357197 |
| concepts[33].level | 2 |
| concepts[33].score | 0.25033190846443176 |
| concepts[33].wikidata | https://www.wikidata.org/wiki/Q5757597 |
| concepts[33].display_name | High memory |
| keywords[0].id | https://openalex.org/keywords/speedup |
| keywords[0].score | 0.8200057148933411 |
| keywords[0].display_name | Speedup |
| keywords[1].id | https://openalex.org/keywords/testbed |
| keywords[1].score | 0.780371367931366 |
| keywords[1].display_name | Testbed |
| keywords[2].id | https://openalex.org/keywords/pci-express |
| keywords[2].score | 0.730304479598999 |
| keywords[2].display_name | PCI Express |
| keywords[3].id | https://openalex.org/keywords/symmetric-multiprocessor-system |
| keywords[3].score | 0.6677523851394653 |
| keywords[3].display_name | Symmetric multiprocessor system |
| keywords[4].id | https://openalex.org/keywords/latency |
| keywords[4].score | 0.4431924521923065 |
| keywords[4].display_name | Latency (audio) |
| keywords[5].id | https://openalex.org/keywords/direct-memory-access |
| keywords[5].score | 0.40952882170677185 |
| keywords[5].display_name | Direct memory access |
| keywords[6].id | https://openalex.org/keywords/exascale-computing |
| keywords[6].score | 0.3911478817462921 |
| keywords[6].display_name | Exascale computing |
| keywords[7].id | https://openalex.org/keywords/central-processing-unit |
| keywords[7].score | 0.38133496046066284 |
| keywords[7].display_name | Central processing unit |
| keywords[8].id | https://openalex.org/keywords/supercomputer |
| keywords[8].score | 0.3804810643196106 |
| keywords[8].display_name | Supercomputer |
| keywords[9].id | https://openalex.org/keywords/unconventional-computing |
| keywords[9].score | 0.3638259172439575 |
| keywords[9].display_name | Unconventional computing |
| language | |
| locations[0].id | pmh:oai:arXiv.org:2511.23011 |
| locations[0].is_oa | True |
| locations[0].source.id | https://openalex.org/S4306400194 |
| locations[0].source.issn | |
| locations[0].source.type | repository |
| locations[0].source.is_oa | True |
| locations[0].source.issn_l | |
| locations[0].source.is_core | False |
| locations[0].source.is_in_doaj | False |
| locations[0].source.display_name | arXiv (Cornell University) |
| locations[0].source.host_organization | https://openalex.org/I205783295 |
| locations[0].source.host_organization_name | Cornell University |
| locations[0].source.host_organization_lineage | https://openalex.org/I205783295 |
| locations[0].license | |
| locations[0].pdf_url | https://arxiv.org/pdf/2511.23011 |
| locations[0].version | submittedVersion |
| locations[0].raw_type | text |
| locations[0].license_id | |
| locations[0].is_accepted | False |
| locations[0].is_published | False |
| locations[0].raw_source_name | |
| locations[0].landing_page_url | http://arxiv.org/abs/2511.23011 |
| indexed_in | arxiv |
| authorships[0].author.id | https://openalex.org/A46678940 |
| authorships[0].author.orcid | |
| authorships[0].author.display_name | Wang, Yanjing |
| authorships[0].author_position | first |
| authorships[0].raw_author_name | Wang, Yanjing |
| authorships[0].is_corresponding | True |
| authorships[1].author.id | https://openalex.org/A2671559289 |
| authorships[1].author.orcid | |
| authorships[1].author.display_name | Wu Lizhou |
| authorships[1].author_position | middle |
| authorships[1].raw_author_name | Wu, Lizhou |
| authorships[1].is_corresponding | False |
| authorships[2].author.id | |
| authorships[2].author.orcid | |
| authorships[2].author.display_name | Gao, Sunfeng |
| authorships[2].author_position | middle |
| authorships[2].raw_author_name | Gao, Sunfeng |
| authorships[2].is_corresponding | False |
| authorships[3].author.id | https://openalex.org/A2350824335 |
| authorships[3].author.orcid | |
| authorships[3].author.display_name | Tang Yibo |
| authorships[3].author_position | middle |
| authorships[3].raw_author_name | Tang, Yibo |
| authorships[3].is_corresponding | False |
| authorships[4].author.id | https://openalex.org/A2125846285 |
| authorships[4].author.orcid | |
| authorships[4].author.display_name | Luo Jun-hui |
| authorships[4].author_position | middle |
| authorships[4].raw_author_name | Luo, Junhui |
| authorships[4].is_corresponding | False |
| authorships[5].author.id | https://openalex.org/A2606011598 |
| authorships[5].author.orcid | |
| authorships[5].author.display_name | Wang Zicong |
| authorships[5].author_position | middle |
| authorships[5].raw_author_name | Wang, Zicong |
| authorships[5].is_corresponding | False |
| authorships[6].author.id | https://openalex.org/A1940107361 |
| authorships[6].author.orcid | https://orcid.org/0000-0002-7267-1968 |
| authorships[6].author.display_name | Ou Yang |
| authorships[6].author_position | middle |
| authorships[6].raw_author_name | Ou, Yang |
| authorships[6].is_corresponding | False |
| authorships[7].author.id | https://openalex.org/A2742238134 |
| authorships[7].author.orcid | |
| authorships[7].author.display_name | Dong, Dezun |
| authorships[7].author_position | middle |
| authorships[7].raw_author_name | Dong, Dezun |
| authorships[7].is_corresponding | False |
| authorships[8].author.id | https://openalex.org/A2131327562 |
| authorships[8].author.orcid | |
| authorships[8].author.display_name | Xiao Nong |
| authorships[8].author_position | middle |
| authorships[8].raw_author_name | Xiao, Nong |
| authorships[8].is_corresponding | False |
| authorships[9].author.id | https://openalex.org/A2088995912 |
| authorships[9].author.orcid | |
| authorships[9].author.display_name | Lai Mingche |
| authorships[9].author_position | last |
| authorships[9].raw_author_name | Lai, Mingche |
| authorships[9].is_corresponding | False |
| has_content.pdf | False |
| has_content.grobid_xml | False |
| is_paratext | False |
| open_access.is_oa | True |
| open_access.oa_url | https://arxiv.org/pdf/2511.23011 |
| open_access.oa_status | green |
| open_access.any_repository_has_fulltext | False |
| created_date | 2025-12-03T00:00:00 |
| display_name | Cohet: A CXL-Driven Coherent Heterogeneous Computing Framework with Hardware-Calibrated Full-System Simulation |
| has_fulltext | False |
| is_retracted | False |
| updated_date | 2025-12-03T00:07:38.036990 |
| primary_topic.id | https://openalex.org/T10054 |
| primary_topic.field.id | https://openalex.org/fields/17 |
| primary_topic.field.display_name | Computer Science |
| primary_topic.score | 0.6027531027793884 |
| primary_topic.domain.id | https://openalex.org/domains/3 |
| primary_topic.domain.display_name | Physical Sciences |
| primary_topic.subfield.id | https://openalex.org/subfields/1708 |
| primary_topic.subfield.display_name | Hardware and Architecture |
| primary_topic.display_name | Parallel Computing and Optimization Techniques |
| cited_by_count | 0 |
| locations_count | 1 |
| best_oa_location.id | pmh:oai:arXiv.org:2511.23011 |
| best_oa_location.is_oa | True |
| best_oa_location.source.id | https://openalex.org/S4306400194 |
| best_oa_location.source.issn | |
| best_oa_location.source.type | repository |
| best_oa_location.source.is_oa | True |
| best_oa_location.source.issn_l | |
| best_oa_location.source.is_core | False |
| best_oa_location.source.is_in_doaj | False |
| best_oa_location.source.display_name | arXiv (Cornell University) |
| best_oa_location.source.host_organization | https://openalex.org/I205783295 |
| best_oa_location.source.host_organization_name | Cornell University |
| best_oa_location.source.host_organization_lineage | https://openalex.org/I205783295 |
| best_oa_location.license | |
| best_oa_location.pdf_url | https://arxiv.org/pdf/2511.23011 |
| best_oa_location.version | submittedVersion |
| best_oa_location.raw_type | text |
| best_oa_location.license_id | |
| best_oa_location.is_accepted | False |
| best_oa_location.is_published | False |
| best_oa_location.raw_source_name | |
| best_oa_location.landing_page_url | http://arxiv.org/abs/2511.23011 |
| primary_location.id | pmh:oai:arXiv.org:2511.23011 |
| primary_location.is_oa | True |
| primary_location.source.id | https://openalex.org/S4306400194 |
| primary_location.source.issn | |
| primary_location.source.type | repository |
| primary_location.source.is_oa | True |
| primary_location.source.issn_l | |
| primary_location.source.is_core | False |
| primary_location.source.is_in_doaj | False |
| primary_location.source.display_name | arXiv (Cornell University) |
| primary_location.source.host_organization | https://openalex.org/I205783295 |
| primary_location.source.host_organization_name | Cornell University |
| primary_location.source.host_organization_lineage | https://openalex.org/I205783295 |
| primary_location.license | |
| primary_location.pdf_url | https://arxiv.org/pdf/2511.23011 |
| primary_location.version | submittedVersion |
| primary_location.raw_type | text |
| primary_location.license_id | |
| primary_location.is_accepted | False |
| primary_location.is_published | False |
| primary_location.raw_source_name | |
| primary_location.landing_page_url | http://arxiv.org/abs/2511.23011 |
| publication_date | 2025-11-28 |
| publication_year | 2025 |
| referenced_works_count | 0 |
| abstract_inverted_index.a | 112, 121, 152, 175, 244 |
| abstract_inverted_index.In | 18 |
| abstract_inverted_index.It | 119 |
| abstract_inverted_index.OS | 134 |
| abstract_inverted_index.To | 145 |
| abstract_inverted_index.an | 186, 253 |
| abstract_inverted_index.at | 210 |
| abstract_inverted_index.by | 71, 199, 204 |
| abstract_inverted_index.in | 37, 66 |
| abstract_inverted_index.is | 159 |
| abstract_inverted_index.of | 61, 74, 142, 161, 190, 221, 256 |
| abstract_inverted_index.on | 5 |
| abstract_inverted_index.to | 54, 103, 125, 207, 239, 246 |
| abstract_inverted_index.we | 149, 217 |
| abstract_inverted_index.3%. | 191 |
| abstract_inverted_index.5.5 | 245 |
| abstract_inverted_index.68% | 200 |
| abstract_inverted_index.CPU | 106, 127 |
| abstract_inverted_index.CXL | 164, 177, 181 |
| abstract_inverted_index.DMA | 208 |
| abstract_inverted_index.Our | 192 |
| abstract_inverted_index.RAO | 250 |
| abstract_inverted_index.RPC | 259 |
| abstract_inverted_index.XPU | 108, 129 |
| abstract_inverted_index.all | 163 |
| abstract_inverted_index.and | 14, 23, 63, 81, 100, 107, 115, 128, 140, 166, 183, 201, 233, 252 |
| abstract_inverted_index.are | 228 |
| abstract_inverted_index.for | 249, 258 |
| abstract_inverted_index.has | 170 |
| abstract_inverted_index.the | 38, 52, 57, 72, 89, 98, 133, 219 |
| abstract_inverted_index.two | 224 |
| abstract_inverted_index.CPUs | 62 |
| abstract_inverted_index.PCIe | 6 |
| abstract_inverted_index.This | 85 |
| abstract_inverted_index.also | 150 |
| abstract_inverted_index.been | 171 |
| abstract_inverted_index.both | 126 |
| abstract_inverted_index.call | 236 |
| abstract_inverted_index.form | 104 |
| abstract_inverted_index.from | 9 |
| abstract_inverted_index.have | 28 |
| abstract_inverted_index.link | 34 |
| abstract_inverted_index.many | 21 |
| abstract_inverted_index.mode | 60 |
| abstract_inverted_index.open | 24 |
| abstract_inverted_index.real | 176 |
| abstract_inverted_index.that | 195 |
| abstract_inverted_index.this | 67 |
| abstract_inverted_index.upon | 214 |
| abstract_inverted_index.with | 136, 179, 223 |
| abstract_inverted_index.(CXL) | 35 |
| abstract_inverted_index.(RAO) | 232 |
| abstract_inverted_index.1.86x | 257 |
| abstract_inverted_index.14.4x | 205 |
| abstract_inverted_index.40.2x | 247 |
| abstract_inverted_index.Cohet | 96, 147, 222 |
| abstract_inverted_index.XPUs, | 64 |
| abstract_inverted_index.after | 41 |
| abstract_inverted_index.among | 30 |
| abstract_inverted_index.apps, | 226 |
| abstract_inverted_index.built | 4 |
| abstract_inverted_index.error | 189 |
| abstract_inverted_index.first | 90 |
| abstract_inverted_index.holds | 51 |
| abstract_inverted_index.named | 156 |
| abstract_inverted_index.paper | 86 |
| abstract_inverted_index.pool. | 118 |
| abstract_inverted_index.pools | 109 |
| abstract_inverted_index.share | 111 |
| abstract_inverted_index.smart | 137 |
| abstract_inverted_index.these | 215 |
| abstract_inverted_index.which | 31, 110, 158, 227 |
| abstract_inverted_index.(RPC). | 237 |
| abstract_inverted_index.Cohet, | 88 |
| abstract_inverted_index.SimCXL | 169 |
| abstract_inverted_index.atomic | 230 |
| abstract_inverted_index.device | 167 |
| abstract_inverted_index.domain | 40 |
| abstract_inverted_index.killer | 225 |
| abstract_inverted_index.memory | 101, 117, 138, 182 |
| abstract_inverted_index.recent | 19 |
| abstract_inverted_index.remote | 229, 234 |
| abstract_inverted_index.single | 113 |
| abstract_inverted_index.suffer | 8 |
| abstract_inverted_index.types. | 168 |
| abstract_inverted_index.years, | 20 |
| abstract_inverted_index.CXL-NIC | 242 |
| abstract_inverted_index.SimCXL, | 157 |
| abstract_inverted_index.against | 174 |
| abstract_inverted_index.average | 187, 254 |
| abstract_inverted_index.capable | 160 |
| abstract_inverted_index.complex | 15 |
| abstract_inverted_index.compute | 32, 99, 130 |
| abstract_inverted_index.dealing | 135 |
| abstract_inverted_index.design, | 241 |
| abstract_inverted_index.exposes | 120 |
| abstract_inverted_index.express | 33 |
| abstract_inverted_index.latency | 198 |
| abstract_inverted_index.leaving | 132 |
| abstract_inverted_index.models. | 17 |
| abstract_inverted_index.present | 151 |
| abstract_inverted_index.reduces | 197 |
| abstract_inverted_index.remains | 69 |
| abstract_inverted_index.reveals | 194 |
| abstract_inverted_index.several | 43 |
| abstract_inverted_index.showing | 185 |
| abstract_inverted_index.speedup | 248, 255 |
| abstract_inverted_index.systems | 3 |
| abstract_inverted_index.testbed | 178 |
| abstract_inverted_index.unclear | 82 |
| abstract_inverted_index.unified | 114 |
| abstract_inverted_index.various | 180 |
| abstract_inverted_index.Although | 46 |
| abstract_inverted_index.Building | 213 |
| abstract_inverted_index.Compared | 238 |
| abstract_inverted_index.PCIe-NIC | 240 |
| abstract_inverted_index.achieves | 243 |
| abstract_inverted_index.benefits | 220 |
| abstract_inverted_index.coherent | 48, 92, 116 |
| abstract_inverted_index.compared | 206 |
| abstract_inverted_index.emerged, | 29 |
| abstract_inverted_index.hampered | 70 |
| abstract_inverted_index.immature | 78 |
| abstract_inverted_index.modeling | 162 |
| abstract_inverted_index.presents | 87 |
| abstract_inverted_index.prevails | 36 |
| abstract_inverted_index.research | 65 |
| abstract_inverted_index.scarcity | 73 |
| abstract_inverted_index.standard | 122 |
| abstract_inverted_index.threads, | 131 |
| abstract_inverted_index.unbiased | 105 |
| abstract_inverted_index.CXL-based | 47 |
| abstract_inverted_index.CXL.cache | 196 |
| abstract_inverted_index.acquiring | 42 |
| abstract_inverted_index.available | 75 |
| abstract_inverted_index.bandwidth | 203 |
| abstract_inverted_index.cacheline | 211 |
| abstract_inverted_index.competing | 44 |
| abstract_inverted_index.computing | 2, 50, 59, 94 |
| abstract_inverted_index.decouples | 97 |
| abstract_inverted_index.direction | 68 |
| abstract_inverted_index.increases | 202 |
| abstract_inverted_index.insights, | 216 |
| abstract_inverted_index.interface | 124 |
| abstract_inverted_index.operation | 231 |
| abstract_inverted_index.potential | 53 |
| abstract_inverted_index.procedure | 235 |
| abstract_inverted_index.research, | 148 |
| abstract_inverted_index.resources | 102 |
| abstract_inverted_index.simulator | 155 |
| abstract_inverted_index.standards | 27 |
| abstract_inverted_index.transfers | 209 |
| abstract_inverted_index.transform | 56 |
| abstract_inverted_index.CXL-driven | 91 |
| abstract_inverted_index.allocation | 139 |
| abstract_inverted_index.calibrated | 173 |
| abstract_inverted_index.evaluation | 193 |
| abstract_inverted_index.facilitate | 146 |
| abstract_inverted_index.framework. | 95 |
| abstract_inverted_index.management | 141 |
| abstract_inverted_index.offloading | 251 |
| abstract_inverted_index.platforms, | 77 |
| abstract_inverted_index.prospects. | 84 |
| abstract_inverted_index.resources. | 144 |
| abstract_inverted_index.rigorously | 172 |
| abstract_inverted_index.simulation | 188 |
| abstract_inverted_index.solutions. | 45 |
| abstract_inverted_index.application | 83 |
| abstract_inverted_index.cycle-level | 154 |
| abstract_inverted_index.demonstrate | 218 |
| abstract_inverted_index.ecosystems, | 80 |
| abstract_inverted_index.full-system | 153 |
| abstract_inverted_index.host-device | 12 |
| abstract_inverted_index.inefficient | 10 |
| abstract_inverted_index.malloc/mmap | 123 |
| abstract_inverted_index.offloading. | 261 |
| abstract_inverted_index.programming | 16 |
| abstract_inverted_index.proprietary | 22 |
| abstract_inverted_index.Conventional | 0 |
| abstract_inverted_index.fine-grained | 11 |
| abstract_inverted_index.granularity. | 212 |
| abstract_inverted_index.interactions | 13 |
| abstract_inverted_index.interconnect | 26 |
| abstract_inverted_index.CXL-supported | 76 |
| abstract_inverted_index.accelerators, | 184 |
| abstract_inverted_index.collaborative | 58 |
| abstract_inverted_index.fundamentally | 55 |
| abstract_inverted_index.heterogeneous | 1, 49, 93, 143 |
| abstract_inverted_index.interconnects | 7 |
| abstract_inverted_index.open-standard | 39 |
| abstract_inverted_index.sub-protocols | 165 |
| abstract_inverted_index.cache-coherent | 25 |
| abstract_inverted_index.(de)serialization | 260 |
| abstract_inverted_index.software/hardware | 79 |
| cited_by_percentile_year | |
| countries_distinct_count | 0 |
| institutions_distinct_count | 10 |
| citation_normalized_percentile.value | 0.86140632 |
| citation_normalized_percentile.is_in_top_1_percent | False |
| citation_normalized_percentile.is_in_top_10_percent | True |