Design and Implementation of an Advanced Radar Signal Processor with Waveform Generator and BIST Unit on a Single FPGA Chip Article Swipe
YOU?
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· 2019
· Open Access
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· DOI: https://doi.org/10.1088/1757-899x/610/1/012095
Field Programmable Gate Arrays (FPGAs) are best suited for signal processing applications that require real-time processing. Therefore, it is preferred over DSP processors in implementing radar receivers that processes incoming continuous stream of data. In the past, implementing complex arithmetic operations in floating point representation was a monopoly on DSP processors and the designers had to work around the sequential nature of the DSP processor to make it suitable for real-time applications by using buffered and multi-clocking designs. But nowadays, the great advances in FPGA design technology minimized this design effort since it is capable of performing these complex algorithms in real time. This paper represents the design and implementation of an advanced radar signal processor for binary phase-coded pulsed radar incorporating a time range side lobes suppression technique on a single FPGA chip. The proposed hardware design includes a waveform generator, an advanced signal processing unit, and a built-in self-test (BIST). Design aspects and hardware details for each part is introduced thoroughly.
Related Topics
- Type
- article
- Language
- en
- Landing Page
- https://doi.org/10.1088/1757-899x/610/1/012095
- OA Status
- diamond
- Cited By
- 2
- References
- 7
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- 10
- OpenAlex ID
- https://openalex.org/W2979564356
Raw OpenAlex JSON
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https://openalex.org/W2979564356Canonical identifier for this work in OpenAlex
- DOI
-
https://doi.org/10.1088/1757-899x/610/1/012095Digital Object Identifier
- Title
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Design and Implementation of an Advanced Radar Signal Processor with Waveform Generator and BIST Unit on a Single FPGA ChipWork title
- Type
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articleOpenAlex work type
- Language
-
enPrimary language
- Publication year
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2019Year of publication
- Publication date
-
2019-09-01Full publication date if available
- Authors
-
Ahmed M. Abdel Razek, Fathy M. Ahmed, Hazem Kamel, Wael Mahfouz, K. MoustafaList of authors in order
- Landing page
-
https://doi.org/10.1088/1757-899x/610/1/012095Publisher landing page
- Open access
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YesWhether a free full text is available
- OA status
-
diamondOpen access status per OpenAlex
- OA URL
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https://doi.org/10.1088/1757-899x/610/1/012095Direct OA link when available
- Concepts
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Digital signal processing, Field-programmable gate array, Computer science, Digital signal processor, Radar, Embedded system, Computer hardware, Chip, Signal processing, TelecommunicationsTop concepts (fields/topics) attached by OpenAlex
- Cited by
-
2Total citation count in OpenAlex
- Citations by year (recent)
-
2024: 1, 2023: 1Per-year citation counts (last 5 years)
- References (count)
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7Number of works referenced by this work
- Related works (count)
-
10Other works algorithmically related by OpenAlex
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| abstract_inverted_index.details | 157 |
| abstract_inverted_index.require | 14 |
| abstract_inverted_index.Abstract | 0 |
| abstract_inverted_index.advanced | 113, 144 |
| abstract_inverted_index.advances | 83 |
| abstract_inverted_index.buffered | 75 |
| abstract_inverted_index.built-in | 150 |
| abstract_inverted_index.designs. | 78 |
| abstract_inverted_index.floating | 43 |
| abstract_inverted_index.hardware | 137, 156 |
| abstract_inverted_index.includes | 139 |
| abstract_inverted_index.incoming | 30 |
| abstract_inverted_index.monopoly | 48 |
| abstract_inverted_index.proposed | 136 |
| abstract_inverted_index.suitable | 69 |
| abstract_inverted_index.waveform | 141 |
| abstract_inverted_index.designers | 54 |
| abstract_inverted_index.minimized | 88 |
| abstract_inverted_index.nowadays, | 80 |
| abstract_inverted_index.preferred | 20 |
| abstract_inverted_index.processes | 29 |
| abstract_inverted_index.processor | 65, 116 |
| abstract_inverted_index.real-time | 15, 71 |
| abstract_inverted_index.receivers | 27 |
| abstract_inverted_index.self-test | 151 |
| abstract_inverted_index.technique | 129 |
| abstract_inverted_index.Therefore, | 17 |
| abstract_inverted_index.algorithms | 100 |
| abstract_inverted_index.arithmetic | 40 |
| abstract_inverted_index.continuous | 31 |
| abstract_inverted_index.generator, | 142 |
| abstract_inverted_index.introduced | 162 |
| abstract_inverted_index.operations | 41 |
| abstract_inverted_index.performing | 97 |
| abstract_inverted_index.processing | 11, 146 |
| abstract_inverted_index.processors | 23, 51 |
| abstract_inverted_index.represents | 106 |
| abstract_inverted_index.sequential | 60 |
| abstract_inverted_index.technology | 87 |
| abstract_inverted_index.phase-coded | 119 |
| abstract_inverted_index.processing. | 16 |
| abstract_inverted_index.suppression | 128 |
| abstract_inverted_index.thoroughly. | 163 |
| abstract_inverted_index.Programmable | 2 |
| abstract_inverted_index.applications | 12, 72 |
| abstract_inverted_index.implementing | 25, 38 |
| abstract_inverted_index.incorporating | 122 |
| abstract_inverted_index.implementation | 110 |
| abstract_inverted_index.multi-clocking | 77 |
| abstract_inverted_index.representation | 45 |
| cited_by_percentile_year.max | 94 |
| cited_by_percentile_year.min | 89 |
| countries_distinct_count | 1 |
| institutions_distinct_count | 5 |
| sustainable_development_goals[0].id | https://metadata.un.org/sdg/7 |
| sustainable_development_goals[0].score | 0.47999998927116394 |
| sustainable_development_goals[0].display_name | Affordable and clean energy |
| citation_normalized_percentile.value | 0.15665236 |
| citation_normalized_percentile.is_in_top_1_percent | False |
| citation_normalized_percentile.is_in_top_10_percent | False |