Exploiting Aging Benefits for the Design of Reliable Drowsy Cache Memories Article Swipe
YOU?
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· 2017
· Open Access
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· DOI: https://doi.org/10.1109/tcad.2017.2729399
In this paper, we show how beneficial effects of aging on static power consumption can be exploited to design reliable drowsy cache memories adopting dynamic voltage scaling (DVS) to reduce static power. First, we develop an analytical model allowing designers to evaluate the long-term threshold voltage degradation induced by bias temperature instability (BTI) in a drowsy cache memory. Through HSPICE simulations, we demonstrate that, as drowsy memories age, static power reduction techniques based on DVS become more effective because of reduction in sub-threshold current due to BTI aging. We develop a simulation framework to evaluate trade-offs between static power and reliability, and a methodology to properly select the “drowsy” data retention voltage. We then propose different architectures of a drowsy cache memory allowing designers to meet different power and reliability constraints. The performed HSPICE simulations show a soft error rate and static noise margin improvement up to 20.8% and 22.7%, respectively, compared to standard aging unaware drowsy technique. This is achieved with a limited static power increase during the very early lifetime, and with static energy saving of up to 37% in 10 years of operation, at no or very limited hardware overhead.
Related Topics
- Type
- article
- Language
- en
- Landing Page
- https://doi.org/10.1109/tcad.2017.2729399
- OA Status
- green
- Cited By
- 15
- References
- 41
- Related Works
- 10
- OpenAlex ID
- https://openalex.org/W2737381876
Raw OpenAlex JSON
- OpenAlex ID
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https://openalex.org/W2737381876Canonical identifier for this work in OpenAlex
- DOI
-
https://doi.org/10.1109/tcad.2017.2729399Digital Object Identifier
- Title
-
Exploiting Aging Benefits for the Design of Reliable Drowsy Cache MemoriesWork title
- Type
-
articleOpenAlex work type
- Language
-
enPrimary language
- Publication year
-
2017Year of publication
- Publication date
-
2017-07-19Full publication date if available
- Authors
-
Daniele Rossi, Vasileios Tenentes, S.M. Reddy, Bashir M. Al‐Hashimi, A.D. BrownList of authors in order
- Landing page
-
https://doi.org/10.1109/tcad.2017.2729399Publisher landing page
- Open access
-
YesWhether a free full text is available
- OA status
-
greenOpen access status per OpenAlex
- OA URL
-
https://hdl.handle.net/2299/20397Direct OA link when available
- Concepts
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Cache, Reliability (semiconductor), Computer science, Overhead (engineering), Reliability engineering, Dynamic voltage scaling, Reduction (mathematics), Subthreshold conduction, Power (physics), Embedded system, Voltage, Static random-access memory, Margin (machine learning), Dynamic demand, Electronic engineering, Engineering, Transistor, Computer hardware, Electrical engineering, Parallel computing, Geometry, Mathematics, Quantum mechanics, Machine learning, Operating system, PhysicsTop concepts (fields/topics) attached by OpenAlex
- Cited by
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15Total citation count in OpenAlex
- Citations by year (recent)
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2023: 2, 2022: 1, 2021: 5, 2020: 1, 2019: 3Per-year citation counts (last 5 years)
- References (count)
-
41Number of works referenced by this work
- Related works (count)
-
10Other works algorithmically related by OpenAlex
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