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International Journal of Recent Technology and Engineering (IJRTE) • Vol 8 • No 2S3
FPGA Implementation of Fault Tolerant Full Adder Design for High Speed VLSI Architectures
August 2019 • Vikas Maheshwari, R. S. Singh
The essential goal is to distinguish and diminish the deficiencies in full Adder configuration making use of Self checking and Self Repairing Adder Block. The tempo of chip disappointment is straightforwardly relative to chip thickness. A framework should be flaw tolerant to diminish the frustration rate. The nearness of different troubles can demolish the usefulness of complete snake. This paper displays a region proficient flaw tolerant complete snake shape that may repair issues without interfering with the eve…
Field-Programmable Gate Array
Computer Science
Very-Large-Scale Integration
Chip-8
Parallel Computing
Arithmetic
Embedded System
Computer Hardware
Mathematics
Social Psychology
Geometry