EFFICIENT HARDWARE ARCHITECTURES FOR MPEG-4 CORE PROFILE Article Swipe
YOU?
·
· 2015
· Open Access
·
· OA: W49213193
Efficient hardware acceleration architectures are proposed for the most demanding MPEG-4 core profile algorithms, namely; tex-ture motion estimation (TME), binary motion estimation (BME) and the shape adaptive discrete cosine transform (SA-DCT). The proposed ME designs may also be used for H.264, since both ar-chitectures can handle variable block sizes. Both ME architec-tures employ early termination techniques that reduce latency and save needless memory accesses and power consumption. They also use a pixel subsampling technique to facilitate parallelism, while balancing the computational load. The BME datapath also saves operations by using Run Length Coded (RLC) pixel address-ing. The SA-DCT module has a re-configuring multiplier-less se-rial datapath using adders and multiplexers only to improve area and power. The SA-DCT packing steps are done using a minimal switching addressing scheme with guarded evaluation. All three modules have been synthesised targeting the WildCard-II FPGA benchmarking platform adopted by the MPEG-4 Part9 reference hardware group. 1.