Parallel Automata Processor Article Swipe
Arun Subramaniyan
,
Reetuparna Das
·
YOU?
·
· 2017
· Open Access
·
· DOI: https://doi.org/10.1145/3140659.3080207
YOU?
·
· 2017
· Open Access
·
· DOI: https://doi.org/10.1145/3140659.3080207
Finite State Machines (FSM) are widely used computation models for many application domains. These embarrassingly sequential applications with irregular memory access patterns perform poorly on conventional von-Neumann architectures. The Micron Automata Processor (AP) is an in-situ memory-based computational architecture that accelerates non-deterministic finite automata (NFA) processing in hardware. However, each FSM on the AP is processed sequentially, limiting potential speedups. In this paper, we explore the FSM parallelization problem in the context of the AP. Extending classical parallelization techniques to NFAs executing on AP is non-trivial because of high state-transition tracking overheads and exponential computation complexity. We present the associated challenges and propose solutions that leverage both the unique properties of the NFAs (connected components, input symbol ranges, convergence, common parent states) and unique features in the AP (support for simultaneous transitions, low-overhead flow switching, state vector cache) to realize parallel NFA execution on the AP. We evaluate our techniques against several important benchmarks including NFAs used for network intrusion detection, malware detection, text processing, protein motif searching, DNA sequencing, and data analytics. Our proposed parallelization scheme demonstrates significant speedup (25.5x on average) compared to sequential execution on AP. Prior work has already shown that sequential execution on AP is at least an order of magnitude better than GPUs, multi-core processors and Xeon Phi accelerator.
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Metadata
- Type
- article
- Language
- en
- Landing Page
- https://doi.org/10.1145/3140659.3080207
- http://dl.acm.org/ft_gateway.cfm?id=3080207&type=pdf
- OA Status
- bronze
- Cited By
- 13
- References
- 30
- Related Works
- 10
- OpenAlex ID
- https://openalex.org/W4240591052
All OpenAlex metadata
Raw OpenAlex JSON
- OpenAlex ID
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https://openalex.org/W4240591052Canonical identifier for this work in OpenAlex
- DOI
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https://doi.org/10.1145/3140659.3080207Digital Object Identifier
- Title
-
Parallel Automata ProcessorWork title
- Type
-
articleOpenAlex work type
- Language
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enPrimary language
- Publication year
-
2017Year of publication
- Publication date
-
2017-06-24Full publication date if available
- Authors
-
Arun Subramaniyan, Reetuparna DasList of authors in order
- Landing page
-
https://doi.org/10.1145/3140659.3080207Publisher landing page
- PDF URL
-
https://dl.acm.org/ft_gateway.cfm?id=3080207&type=pdfDirect link to full text PDF
- Open access
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YesWhether a free full text is available
- OA status
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bronzeOpen access status per OpenAlex
- OA URL
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https://dl.acm.org/ft_gateway.cfm?id=3080207&type=pdfDirect OA link when available
- Concepts
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Computer science, Parallel computing, Speedup, Finite-state machine, Xeon Phi, Xeon, Theoretical computer science, AlgorithmTop concepts (fields/topics) attached by OpenAlex
- Cited by
-
13Total citation count in OpenAlex
- Citations by year (recent)
-
2025: 1, 2024: 1, 2021: 3, 2020: 4, 2019: 1Per-year citation counts (last 5 years)
- References (count)
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30Number of works referenced by this work
- Related works (count)
-
10Other works algorithmically related by OpenAlex
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| abstract_inverted_index.intrusion | 159 |
| abstract_inverted_index.irregular | 18 |
| abstract_inverted_index.magnitude | 205 |
| abstract_inverted_index.overheads | 91 |
| abstract_inverted_index.potential | 58 |
| abstract_inverted_index.processed | 55 |
| abstract_inverted_index.solutions | 103 |
| abstract_inverted_index.speedups. | 59 |
| abstract_inverted_index.(connected | 113 |
| abstract_inverted_index.analytics. | 172 |
| abstract_inverted_index.associated | 99 |
| abstract_inverted_index.benchmarks | 153 |
| abstract_inverted_index.challenges | 100 |
| abstract_inverted_index.detection, | 160, 162 |
| abstract_inverted_index.multi-core | 209 |
| abstract_inverted_index.processing | 45 |
| abstract_inverted_index.processors | 210 |
| abstract_inverted_index.properties | 109 |
| abstract_inverted_index.searching, | 167 |
| abstract_inverted_index.sequential | 15, 185, 195 |
| abstract_inverted_index.switching, | 134 |
| abstract_inverted_index.techniques | 78, 149 |
| abstract_inverted_index.accelerates | 40 |
| abstract_inverted_index.application | 11 |
| abstract_inverted_index.complexity. | 95 |
| abstract_inverted_index.components, | 114 |
| abstract_inverted_index.computation | 7, 94 |
| abstract_inverted_index.exponential | 93 |
| abstract_inverted_index.non-trivial | 85 |
| abstract_inverted_index.processing, | 164 |
| abstract_inverted_index.sequencing, | 169 |
| abstract_inverted_index.significant | 178 |
| abstract_inverted_index.von-Neumann | 26 |
| abstract_inverted_index.accelerator. | 214 |
| abstract_inverted_index.applications | 16 |
| abstract_inverted_index.architecture | 38 |
| abstract_inverted_index.conventional | 25 |
| abstract_inverted_index.convergence, | 118 |
| abstract_inverted_index.demonstrates | 177 |
| abstract_inverted_index.low-overhead | 132 |
| abstract_inverted_index.memory-based | 36 |
| abstract_inverted_index.simultaneous | 130 |
| abstract_inverted_index.transitions, | 131 |
| abstract_inverted_index.computational | 37 |
| abstract_inverted_index.sequentially, | 56 |
| abstract_inverted_index.architectures. | 27 |
| abstract_inverted_index.embarrassingly | 14 |
| abstract_inverted_index.parallelization | 67, 77, 175 |
| abstract_inverted_index.state-transition | 89 |
| abstract_inverted_index.non-deterministic | 41 |
| cited_by_percentile_year.max | 97 |
| cited_by_percentile_year.min | 90 |
| countries_distinct_count | 1 |
| institutions_distinct_count | 2 |
| citation_normalized_percentile.value | 0.87590806 |
| citation_normalized_percentile.is_in_top_1_percent | False |
| citation_normalized_percentile.is_in_top_10_percent | False |