Real-Time Simulation of Passage-of-Time Encoding in Cerebellum Using a Scalable FPGA-Based System Article Swipe
Junwen Luo
,
Graeme Coapes
,
Terrence Mak
,
Tadashi Yamazaki
,
Chung Tin
,
Patrick Degenaar
·
YOU?
·
· 2015
· Open Access
·
· DOI: https://doi.org/10.1109/tbcas.2015.2460232
YOU?
·
· 2015
· Open Access
·
· DOI: https://doi.org/10.1109/tbcas.2015.2460232
The cerebellum plays a critical role for sensorimotor control and learning. However, dysmetria or delays in movements' onsets consequent to damages in cerebellum cannot be cured completely at the moment. Neuroprosthesis is an emerging technology that can potentially substitute such motor control module in the brain. A pre-requisite for this to become practical is the capability to simulate the cerebellum model in real-time, with low timing distortion for proper interfacing with the biological system. In this paper, we present a frame-based network-on-chip (NoC) hardware architecture for implementing a bio-realistic cerebellum model with ∼ 100 000 neurons, which has been used for studying timing control or passage-of-time (POT) encoding mediated by the cerebellum. The simulation results verify that our implementation reproduces the POT representation by the cerebellum properly. Furthermore, our field-programmable gate array (FPGA)-based system demonstrates excellent computational speed that it can complete 1sec real world activities within 25.6 ms. It is also highly scalable such that it can maintain approximately the same computational speed even if the neuron number increases by one order of magnitude. Our design is shown to outperform three alternative approaches previously used for implementing spiking neural network model. Finally, we show a hardware electronic setup and illustrate how the silicon cerebellum can be adapted as a potential neuroprosthetic platform for future biological or clinical application.
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Metadata
- Type
- article
- Language
- en
- Landing Page
- https://doi.org/10.1109/tbcas.2015.2460232
- OA Status
- hybrid
- Cited By
- 44
- References
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- Related Works
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- OpenAlex ID
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All OpenAlex metadata
Raw OpenAlex JSON
- OpenAlex ID
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https://openalex.org/W1857448332Canonical identifier for this work in OpenAlex
- DOI
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https://doi.org/10.1109/tbcas.2015.2460232Digital Object Identifier
- Title
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Real-Time Simulation of Passage-of-Time Encoding in Cerebellum Using a Scalable FPGA-Based SystemWork title
- Type
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articleOpenAlex work type
- Language
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enPrimary language
- Publication year
-
2015Year of publication
- Publication date
-
2015-10-06Full publication date if available
- Authors
-
Junwen Luo, Graeme Coapes, Terrence Mak, Tadashi Yamazaki, Chung Tin, Patrick DegenaarList of authors in order
- Landing page
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https://doi.org/10.1109/tbcas.2015.2460232Publisher landing page
- Open access
-
YesWhether a free full text is available
- OA status
-
hybridOpen access status per OpenAlex
- OA URL
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https://doi.org/10.1109/tbcas.2015.2460232Direct OA link when available
- Concepts
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Computer science, Interfacing, Field-programmable gate array, Scalability, Spiking neural network, Dysmetria, Cerebellum, Encoding (memory), Neuromorphic engineering, Computer hardware, Artificial neural network, Computer architecture, Embedded system, Artificial intelligence, Neuroscience, Biology, DatabaseTop concepts (fields/topics) attached by OpenAlex
- Cited by
-
44Total citation count in OpenAlex
- Citations by year (recent)
-
2025: 1, 2024: 4, 2023: 8, 2022: 5, 2021: 4Per-year citation counts (last 5 years)
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46Number of works referenced by this work
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10Other works algorithmically related by OpenAlex
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