SLAP: a Split Latency Adaptive VLIW Pipeline Architecture Which Enables on-The-Fly Variable SIMD Vector-Length Article Swipe
Ashish Shrivastava
,
Alan Gatherer
,
Tong Sun
,
Sushma Wokhlu
,
Alex Chandra
·
YOU?
·
· 2021
· Open Access
·
· DOI: https://doi.org/10.1109/icassp39728.2021.9413371
YOU?
·
· 2021
· Open Access
·
· DOI: https://doi.org/10.1109/icassp39728.2021.9413371
Over the last decade the relative latency of access to shared memory by multicore increased as wire resistance dominated latency and low wire density layout pushed multiport memories farther away from their ports. Various techniques were deployed to improve average memory access latencies, such as speculative pre-fetching and branch-prediction, often leading to high variance in execution time which is unacceptable in real time systems. Smart DMAs can be used to directly copy data into a layer1 SRAM, but with overhead. The VLIW architecture, the de facto signal processing engine, suffers badly from a breakdown in lockstep execution of scalar and vector instructions. We describe the Split Latency Adaptive Pipeline (SLAP) VLIW architecture, a cache performance improvement technology that requires zero change to object code, while removing smart DMAs and their overhead. SLAP builds on the Decoupled Access and Execute concept by 1) breaking lockstep execution of functional units, 2) enabling variable vector length for variable data level parallelism, and 3) adding a novel triangular load mechanism. We discuss the SLAP architecture and demonstrate the performance benefits on real traces from a wireless baseband system (where even the most compute intensive functions suffer from an Amdahls law limitation due to a mixture of scalar and vector processing).
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Metadata
- Type
- preprint
- Language
- en
- Landing Page
- https://doi.org/10.1109/icassp39728.2021.9413371
- OA Status
- green
- References
- 12
- Related Works
- 20
- OpenAlex ID
- https://openalex.org/W3135195651
All OpenAlex metadata
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https://openalex.org/W3135195651Canonical identifier for this work in OpenAlex
- DOI
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https://doi.org/10.1109/icassp39728.2021.9413371Digital Object Identifier
- Title
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SLAP: a Split Latency Adaptive VLIW Pipeline Architecture Which Enables on-The-Fly Variable SIMD Vector-LengthWork title
- Type
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preprintOpenAlex work type
- Language
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enPrimary language
- Publication year
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2021Year of publication
- Publication date
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2021-05-13Full publication date if available
- Authors
-
Ashish Shrivastava, Alan Gatherer, Tong Sun, Sushma Wokhlu, Alex ChandraList of authors in order
- Landing page
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https://doi.org/10.1109/icassp39728.2021.9413371Publisher landing page
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YesWhether a free full text is available
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greenOpen access status per OpenAlex
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https://arxiv.org/pdf/2102.13301Direct OA link when available
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Computer science, Very long instruction word, Parallel computing, Cache, Latency (audio), SIMD, Pipeline (software), Embedded system, Operating system, TelecommunicationsTop concepts (fields/topics) attached by OpenAlex
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0Total citation count in OpenAlex
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20Other works algorithmically related by OpenAlex
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| abstract_inverted_index.even | 185 |
| abstract_inverted_index.from | 30, 91, 179, 192 |
| abstract_inverted_index.high | 52 |
| abstract_inverted_index.into | 73 |
| abstract_inverted_index.last | 2 |
| abstract_inverted_index.load | 164 |
| abstract_inverted_index.most | 187 |
| abstract_inverted_index.real | 61, 177 |
| abstract_inverted_index.such | 43 |
| abstract_inverted_index.that | 117 |
| abstract_inverted_index.time | 56, 62 |
| abstract_inverted_index.used | 68 |
| abstract_inverted_index.were | 35 |
| abstract_inverted_index.wire | 16, 22 |
| abstract_inverted_index.with | 78 |
| abstract_inverted_index.zero | 119 |
| abstract_inverted_index.SRAM, | 76 |
| abstract_inverted_index.Smart | 64 |
| abstract_inverted_index.Split | 105 |
| abstract_inverted_index.badly | 90 |
| abstract_inverted_index.cache | 113 |
| abstract_inverted_index.code, | 123 |
| abstract_inverted_index.facto | 85 |
| abstract_inverted_index.level | 156 |
| abstract_inverted_index.novel | 162 |
| abstract_inverted_index.often | 49 |
| abstract_inverted_index.smart | 126 |
| abstract_inverted_index.their | 31, 129 |
| abstract_inverted_index.which | 57 |
| abstract_inverted_index.while | 124 |
| abstract_inverted_index.(SLAP) | 109 |
| abstract_inverted_index.(where | 184 |
| abstract_inverted_index.Access | 136 |
| abstract_inverted_index.access | 8, 41 |
| abstract_inverted_index.adding | 160 |
| abstract_inverted_index.builds | 132 |
| abstract_inverted_index.change | 120 |
| abstract_inverted_index.decade | 3 |
| abstract_inverted_index.layer1 | 75 |
| abstract_inverted_index.layout | 24 |
| abstract_inverted_index.length | 152 |
| abstract_inverted_index.memory | 11, 40 |
| abstract_inverted_index.object | 122 |
| abstract_inverted_index.ports. | 32 |
| abstract_inverted_index.pushed | 25 |
| abstract_inverted_index.scalar | 98, 202 |
| abstract_inverted_index.shared | 10 |
| abstract_inverted_index.signal | 86 |
| abstract_inverted_index.suffer | 191 |
| abstract_inverted_index.system | 183 |
| abstract_inverted_index.traces | 178 |
| abstract_inverted_index.units, | 147 |
| abstract_inverted_index.vector | 100, 151, 204 |
| abstract_inverted_index.Amdahls | 194 |
| abstract_inverted_index.Execute | 138 |
| abstract_inverted_index.Latency | 106 |
| abstract_inverted_index.Various | 33 |
| abstract_inverted_index.average | 39 |
| abstract_inverted_index.compute | 188 |
| abstract_inverted_index.concept | 139 |
| abstract_inverted_index.density | 23 |
| abstract_inverted_index.discuss | 167 |
| abstract_inverted_index.engine, | 88 |
| abstract_inverted_index.farther | 28 |
| abstract_inverted_index.improve | 38 |
| abstract_inverted_index.latency | 6, 19 |
| abstract_inverted_index.leading | 50 |
| abstract_inverted_index.mixture | 200 |
| abstract_inverted_index.suffers | 89 |
| abstract_inverted_index.Adaptive | 107 |
| abstract_inverted_index.Pipeline | 108 |
| abstract_inverted_index.baseband | 182 |
| abstract_inverted_index.benefits | 175 |
| abstract_inverted_index.breaking | 142 |
| abstract_inverted_index.deployed | 36 |
| abstract_inverted_index.describe | 103 |
| abstract_inverted_index.directly | 70 |
| abstract_inverted_index.enabling | 149 |
| abstract_inverted_index.lockstep | 95, 143 |
| abstract_inverted_index.memories | 27 |
| abstract_inverted_index.relative | 5 |
| abstract_inverted_index.removing | 125 |
| abstract_inverted_index.requires | 118 |
| abstract_inverted_index.systems. | 63 |
| abstract_inverted_index.variable | 150, 154 |
| abstract_inverted_index.variance | 53 |
| abstract_inverted_index.wireless | 181 |
| abstract_inverted_index.Decoupled | 135 |
| abstract_inverted_index.breakdown | 93 |
| abstract_inverted_index.dominated | 18 |
| abstract_inverted_index.execution | 55, 96, 144 |
| abstract_inverted_index.functions | 190 |
| abstract_inverted_index.increased | 14 |
| abstract_inverted_index.intensive | 189 |
| abstract_inverted_index.multicore | 13 |
| abstract_inverted_index.multiport | 26 |
| abstract_inverted_index.overhead. | 79, 130 |
| abstract_inverted_index.functional | 146 |
| abstract_inverted_index.latencies, | 42 |
| abstract_inverted_index.limitation | 196 |
| abstract_inverted_index.mechanism. | 165 |
| abstract_inverted_index.processing | 87 |
| abstract_inverted_index.resistance | 17 |
| abstract_inverted_index.techniques | 34 |
| abstract_inverted_index.technology | 116 |
| abstract_inverted_index.triangular | 163 |
| abstract_inverted_index.demonstrate | 172 |
| abstract_inverted_index.improvement | 115 |
| abstract_inverted_index.performance | 114, 174 |
| abstract_inverted_index.speculative | 45 |
| abstract_inverted_index.architecture | 170 |
| abstract_inverted_index.parallelism, | 157 |
| abstract_inverted_index.pre-fetching | 46 |
| abstract_inverted_index.processing). | 205 |
| abstract_inverted_index.unacceptable | 59 |
| abstract_inverted_index.architecture, | 82, 111 |
| abstract_inverted_index.instructions. | 101 |
| abstract_inverted_index.branch-prediction, | 48 |
| cited_by_percentile_year | |
| countries_distinct_count | 1 |
| institutions_distinct_count | 5 |
| citation_normalized_percentile.value | 0.02688089 |
| citation_normalized_percentile.is_in_top_1_percent | False |
| citation_normalized_percentile.is_in_top_10_percent | False |