SLAP: A Split Latency Adaptive VLIW pipeline architecture which enables\n on-the-fly variable SIMD vector-length Article Swipe

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Ashish Shrivastava , Alan Gatherer , Tong Sun , Sushma Wokhlu , Alex Chandra ·

YOU? · · 2021 · Open Access · · DOI: https://doi.org/10.48550/arxiv.2102.13301

Over the last decade the relative latency of access to shared memory by\nmulticore increased as wire resistance dominated latency and low wire density\nlayout pushed multiport memories farther away from their ports. Various\ntechniques were deployed to improve average memory access latencies, such as\nspeculative pre-fetching and branch-prediction, often leading to high variance\nin execution time which is unacceptable in real time systems. Smart DMAs can be\nused to directly copy data into a layer1 SRAM, but with overhead. The VLIW\narchitecture, the de facto signal processing engine, suffers badly from a\nbreakdown in lockstep execution of scalar and vector instructions. We describe\nthe Split Latency Adaptive Pipeline (SLAP) VLIW architecture, a cache\nperformance improvement technology that requires zero change to object code,\nwhile removing smart DMAs and their overhead. SLAP builds on the Decoupled\nAccess and Execute concept by 1) breaking lockstep execution of functional\nunits, 2) enabling variable vector length for variable data level parallelism,\nand 3) adding a novel triangular load mechanism. We discuss the SLAP\narchitecture and demonstrate the performance benefits on real traces from a\nwireless baseband system (where even the most compute intensive functions\nsuffer from an Amdahls law limitation due to a mixture of scalar and vector\nprocessing).\n

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Very long instruction word Computer science Parallel computing Cache Latency (audio) Pipeline (software) SIMD Embedded system Operating system Telecommunications

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Type: preprint
Language: en
Landing Page: http://arxiv.org/abs/2102.13301
PDF: https://arxiv.org/pdf/2102.13301
OA Status: green
Related Works: 10
OpenAlex ID: https://openalex.org/W4287323403

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OpenAlex ID: https://openalex.org/W4287323403

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DOI: https://doi.org/10.48550/arxiv.2102.13301

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Title: SLAP: A Split Latency Adaptive VLIW pipeline architecture which enables\n on-the-fly variable SIMD vector-length

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Type: preprint

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Language: en

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Publication year: 2021

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Publication date: 2021-02-25

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Authors: Ashish Shrivastava, Alan Gatherer, Tong Sun, Sushma Wokhlu, Alex Chandra

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Landing page: https://arxiv.org/abs/2102.13301

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PDF URL: https://arxiv.org/pdf/2102.13301

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Concepts: Very long instruction word, Computer science, Parallel computing, Cache, Latency (audio), Pipeline (software), SIMD, Embedded system, Operating system, Telecommunications

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