Vertical Self‐Rectifying Memristive Arrays for Page‐Wise Parallel Logic and Arithmetic Processing Article Swipe
Kunhee Son
,
Jea Min Cho
,
Dong Hoon Shin
,
Yeong-Rok Kim
,
Néstor Ghenzi
,
Sun-Woo Cheong
,
Byeong-su Kim
,
Jung-Kyu Lee
,
Sungho Kim
,
Wonho Choi
,
Soo Hyung Lee
,
Janguk Han
,
Cheol Seong Hwang
,
Kunhee Son
,
Jea Min Cho
,
Dong Hoon Shin
,
Yeong-Rok Kim
,
Néstor Ghenzi
,
Sun-Woo Cheong
,
Byeong-su Kim
,
Jung-Kyu Lee
,
Sungho Kim
,
Wonho Choi
,
Soo Hyung Lee
,
Janguk Han
,
Cheol Seong Hwang
·
YOU?
·
· 2025
· Open Access
·
· DOI: https://doi.org/10.1002/adma.202514099
YOU?
·
· 2025
· Open Access
·
· DOI: https://doi.org/10.1002/adma.202514099
Logic‐in‐memory (LIM) architectures are explored to address the data transfer bottleneck of conventional von Neumann architectures by integrating computation directly within memory arrays. Among various candidates, memristor‐based LIM systems have gained significant attention due to their non‐volatile switching behavior and compatibility with dense integration. In this work, a page‐wise LIM architecture is implemented using a 3D vertical resistive random‐access memory array composed of self‐rectifying Pt–Ta 2 O 5 –Al:HfO 2 –TiN memristors. Two logic primitives—1 M and 2 M logic—are employed to perform intra‐page and inter‐page operations, respectively, enabling core Boolean functions to be executed entirely within the array through resistive state transitions. Based on these logic operations, a memristive arithmetic logic unit (mALU) is designed to perform essential arithmetic functions, including addition, subtraction, increment, and decrement. Owing to the vertical structure of vertical resistive random‐access memory, a 2‐bit full adder is implemented with a footprint of only three cells and completed in 12 steps. The proposed intra‐and inter‐page operations, along with complete mALU functionality, are experimentally demonstrated with high reproducibility. Combined with significantly reduced spatiotemporal cost, these results highlight the promise of this architecture for scalable and energy‐efficient in‐memory computing.
Related Topics
Concepts
Von Neumann architecture
Arithmetic logic unit
Bottleneck
Computer science
Adder
Scalability
Resistive touchscreen
Parallel computing
Logic gate
Memory footprint
Computer architecture
Computation
Logic family
Arithmetic
Computer hardware
Unconventional computing
Architecture
Logic synthesis
Neuromorphic engineering
Memory architecture
Array data structure
In-Memory Processing
Programmable logic device
Non-volatile memory
Boolean function
AND gate
Parallel processing
Electronic engineering
High memory
Resistive random-access memory
Logic optimization
Single-core
Metadata
- Type
- article
- Language
- en
- Landing Page
- https://doi.org/10.1002/adma.202514099
- https://onlinelibrary.wiley.com/doi/pdfdirect/10.1002/adma.202514099
- OA Status
- hybrid
- References
- 38
- OpenAlex ID
- https://openalex.org/W7106537387
All OpenAlex metadata
Raw OpenAlex JSON
- OpenAlex ID
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https://openalex.org/W7106537387Canonical identifier for this work in OpenAlex
- DOI
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https://doi.org/10.1002/adma.202514099Digital Object Identifier
- Title
-
Vertical Self‐Rectifying Memristive Arrays for Page‐Wise Parallel Logic and Arithmetic ProcessingWork title
- Type
-
articleOpenAlex work type
- Language
-
enPrimary language
- Publication year
-
2025Year of publication
- Publication date
-
2025-11-24Full publication date if available
- Authors
-
Kunhee Son, Jea Min Cho, Dong Hoon Shin, Yeong-Rok Kim, Néstor Ghenzi, Sun-Woo Cheong, Byeong-su Kim, Jung-Kyu Lee, Sungho Kim, Wonho Choi, Soo Hyung Lee, Janguk Han, Cheol Seong Hwang, Kunhee Son, Jea Min Cho, Dong Hoon Shin, Yeong-Rok Kim, Néstor Ghenzi, Sun-Woo Cheong, Byeong-su Kim, Jung-Kyu Lee, Sungho Kim, Wonho Choi, Soo Hyung Lee, Janguk Han, Cheol Seong HwangList of authors in order
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https://doi.org/10.1002/adma.202514099Publisher landing page
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https://onlinelibrary.wiley.com/doi/pdfdirect/10.1002/adma.202514099Direct link to full text PDF
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YesWhether a free full text is available
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hybridOpen access status per OpenAlex
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https://onlinelibrary.wiley.com/doi/pdfdirect/10.1002/adma.202514099Direct OA link when available
- Concepts
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Von Neumann architecture, Arithmetic logic unit, Bottleneck, Computer science, Adder, Scalability, Resistive touchscreen, Parallel computing, Logic gate, Memory footprint, Computer architecture, Computation, Logic family, Arithmetic, Computer hardware, Unconventional computing, Architecture, Logic synthesis, Neuromorphic engineering, Memory architecture, Array data structure, In-Memory Processing, Programmable logic device, Non-volatile memory, Boolean function, AND gate, Parallel processing, Electronic engineering, High memory, Resistive random-access memory, Logic optimization, Single-coreTop concepts (fields/topics) attached by OpenAlex
- Cited by
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0Total citation count in OpenAlex
- References (count)
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38Number of works referenced by this work
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