XNOR-VSH: A Valley-Spin Hall Effect-Based Compact and Energy-Efficient Synaptic Crossbar Array for Binary Neural Networks Article Swipe
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· 2023
· Open Access
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· DOI: https://doi.org/10.1109/jxcdc.2023.3320677
Binary neural networks (BNNs) have shown an immense promise for resource-constrained edge artificial intelligence (AI) platforms. However, prior designs typically either require two bit-cells to encode signed weights leading to an area overhead, or require complex peripheral circuitry. In this article, we address this issue by proposing a compact and low power in-memory computing (IMC) of XNOR-based dot products featuring signed weight encoding in a single bit-cell. Our approach utilizes valley-spin Hall (VSH) effect in monolayer tungsten di-selenide to design an XNOR bit-cell (named “XNOR-VSH”) with differential storage and access-transistor-less topology. We co-optimize the proposed VSH device and a memory array to enable robust in-memory dot product computations between signed binary inputs and signed binary weights with sense margin (SM). Our results show that the proposed XNOR-VSH array achieves 4.8%–9.0% and 37%–63% lower IMC latency and energy, respectively, with 49%–64% smaller area compared to spin-transfer-torque (STT)-magnetic random access memory (MRAM) and spin-orbit-torque (SOT)-MRAM based XNOR-arrays. We also present the impact of hardware non-idealities and process variations in XNOR-VSH on system-level accuracy for the trained ResNet-18 BNNs using the CIFAR-10 dataset.
Related Topics
- Type
- article
- Language
- en
- Landing Page
- https://doi.org/10.1109/jxcdc.2023.3320677
- https://ieeexplore.ieee.org/ielx7/6570653/7076742/10268108.pdf
- OA Status
- gold
- Cited By
- 5
- References
- 28
- Related Works
- 10
- OpenAlex ID
- https://openalex.org/W4387197032
Raw OpenAlex JSON
- OpenAlex ID
-
https://openalex.org/W4387197032Canonical identifier for this work in OpenAlex
- DOI
-
https://doi.org/10.1109/jxcdc.2023.3320677Digital Object Identifier
- Title
-
XNOR-VSH: A Valley-Spin Hall Effect-Based Compact and Energy-Efficient Synaptic Crossbar Array for Binary Neural NetworksWork title
- Type
-
articleOpenAlex work type
- Language
-
enPrimary language
- Publication year
-
2023Year of publication
- Publication date
-
2023-09-29Full publication date if available
- Authors
-
Karam Cho, Akul Malhotra, Sumeet Kumar GuptaList of authors in order
- Landing page
-
https://doi.org/10.1109/jxcdc.2023.3320677Publisher landing page
- PDF URL
-
https://ieeexplore.ieee.org/ielx7/6570653/7076742/10268108.pdfDirect link to full text PDF
- Open access
-
YesWhether a free full text is available
- OA status
-
goldOpen access status per OpenAlex
- OA URL
-
https://ieeexplore.ieee.org/ielx7/6570653/7076742/10268108.pdfDirect OA link when available
- Concepts
-
XNOR gate, Computer science, Encoding (memory), Binary number, Topology (electrical circuits), Computer hardware, Logic gate, Electrical engineering, Artificial intelligence, Algorithm, NAND gate, Engineering, Mathematics, ArithmeticTop concepts (fields/topics) attached by OpenAlex
- Cited by
-
5Total citation count in OpenAlex
- Citations by year (recent)
-
2025: 2, 2024: 2, 2023: 1Per-year citation counts (last 5 years)
- References (count)
-
28Number of works referenced by this work
- Related works (count)
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10Other works algorithmically related by OpenAlex
Full payload
| id | https://openalex.org/W4387197032 |
|---|---|
| doi | https://doi.org/10.1109/jxcdc.2023.3320677 |
| ids.doi | https://doi.org/10.1109/jxcdc.2023.3320677 |
| ids.openalex | https://openalex.org/W4387197032 |
| fwci | 0.82941949 |
| type | article |
| title | XNOR-VSH: A Valley-Spin Hall Effect-Based Compact and Energy-Efficient Synaptic Crossbar Array for Binary Neural Networks |
| awards[0].id | https://openalex.org/G6559487808 |
| awards[0].funder_id | https://openalex.org/F4320332180 |
| awards[0].display_name | |
| awards[0].funder_award_id | 13001258 |
| awards[0].funder_display_name | Defense Advanced Research Projects Agency |
| awards[1].id | https://openalex.org/G6839413216 |
| awards[1].funder_id | https://openalex.org/F4320306087 |
| awards[1].display_name | |
| awards[1].funder_award_id | 70NANB17H041 |
| awards[1].funder_display_name | Semiconductor Research Corporation |
| biblio.issue | 2 |
| biblio.volume | 9 |
| biblio.last_page | 107 |
| biblio.first_page | 99 |
| topics[0].id | https://openalex.org/T10502 |
| topics[0].field.id | https://openalex.org/fields/22 |
| topics[0].field.display_name | Engineering |
| topics[0].score | 1.0 |
| topics[0].domain.id | https://openalex.org/domains/3 |
| topics[0].domain.display_name | Physical Sciences |
| topics[0].subfield.id | https://openalex.org/subfields/2208 |
| topics[0].subfield.display_name | Electrical and Electronic Engineering |
| topics[0].display_name | Advanced Memory and Neural Computing |
| topics[1].id | https://openalex.org/T12808 |
| topics[1].field.id | https://openalex.org/fields/22 |
| topics[1].field.display_name | Engineering |
| topics[1].score | 0.9998999834060669 |
| topics[1].domain.id | https://openalex.org/domains/3 |
| topics[1].domain.display_name | Physical Sciences |
| topics[1].subfield.id | https://openalex.org/subfields/2208 |
| topics[1].subfield.display_name | Electrical and Electronic Engineering |
| topics[1].display_name | Ferroelectric and Negative Capacitance Devices |
| topics[2].id | https://openalex.org/T10049 |
| topics[2].field.id | https://openalex.org/fields/31 |
| topics[2].field.display_name | Physics and Astronomy |
| topics[2].score | 0.9990000128746033 |
| topics[2].domain.id | https://openalex.org/domains/3 |
| topics[2].domain.display_name | Physical Sciences |
| topics[2].subfield.id | https://openalex.org/subfields/3107 |
| topics[2].subfield.display_name | Atomic and Molecular Physics, and Optics |
| topics[2].display_name | Magnetic properties of thin films |
| funders[0].id | https://openalex.org/F4320306087 |
| funders[0].ror | https://ror.org/047z4n946 |
| funders[0].display_name | Semiconductor Research Corporation |
| funders[1].id | https://openalex.org/F4320332180 |
| funders[1].ror | https://ror.org/02caytj08 |
| funders[1].display_name | Defense Advanced Research Projects Agency |
| is_xpac | False |
| apc_list.value | 1350 |
| apc_list.currency | USD |
| apc_list.value_usd | 1350 |
| apc_paid.value | 1350 |
| apc_paid.currency | USD |
| apc_paid.value_usd | 1350 |
| concepts[0].id | https://openalex.org/C57684291 |
| concepts[0].level | 4 |
| concepts[0].score | 0.8935666084289551 |
| concepts[0].wikidata | https://www.wikidata.org/wiki/Q1336142 |
| concepts[0].display_name | XNOR gate |
| concepts[1].id | https://openalex.org/C41008148 |
| concepts[1].level | 0 |
| concepts[1].score | 0.5862815976142883 |
| concepts[1].wikidata | https://www.wikidata.org/wiki/Q21198 |
| concepts[1].display_name | Computer science |
| concepts[2].id | https://openalex.org/C125411270 |
| concepts[2].level | 2 |
| concepts[2].score | 0.5504317879676819 |
| concepts[2].wikidata | https://www.wikidata.org/wiki/Q18653 |
| concepts[2].display_name | Encoding (memory) |
| concepts[3].id | https://openalex.org/C48372109 |
| concepts[3].level | 2 |
| concepts[3].score | 0.4641405940055847 |
| concepts[3].wikidata | https://www.wikidata.org/wiki/Q3913 |
| concepts[3].display_name | Binary number |
| concepts[4].id | https://openalex.org/C184720557 |
| concepts[4].level | 2 |
| concepts[4].score | 0.4235374331474304 |
| concepts[4].wikidata | https://www.wikidata.org/wiki/Q7825049 |
| concepts[4].display_name | Topology (electrical circuits) |
| concepts[5].id | https://openalex.org/C9390403 |
| concepts[5].level | 1 |
| concepts[5].score | 0.3665306270122528 |
| concepts[5].wikidata | https://www.wikidata.org/wiki/Q3966 |
| concepts[5].display_name | Computer hardware |
| concepts[6].id | https://openalex.org/C131017901 |
| concepts[6].level | 2 |
| concepts[6].score | 0.2605476379394531 |
| concepts[6].wikidata | https://www.wikidata.org/wiki/Q170451 |
| concepts[6].display_name | Logic gate |
| concepts[7].id | https://openalex.org/C119599485 |
| concepts[7].level | 1 |
| concepts[7].score | 0.21678516268730164 |
| concepts[7].wikidata | https://www.wikidata.org/wiki/Q43035 |
| concepts[7].display_name | Electrical engineering |
| concepts[8].id | https://openalex.org/C154945302 |
| concepts[8].level | 1 |
| concepts[8].score | 0.19573771953582764 |
| concepts[8].wikidata | https://www.wikidata.org/wiki/Q11660 |
| concepts[8].display_name | Artificial intelligence |
| concepts[9].id | https://openalex.org/C11413529 |
| concepts[9].level | 1 |
| concepts[9].score | 0.18437868356704712 |
| concepts[9].wikidata | https://www.wikidata.org/wiki/Q8366 |
| concepts[9].display_name | Algorithm |
| concepts[10].id | https://openalex.org/C124296912 |
| concepts[10].level | 3 |
| concepts[10].score | 0.17842474579811096 |
| concepts[10].wikidata | https://www.wikidata.org/wiki/Q575178 |
| concepts[10].display_name | NAND gate |
| concepts[11].id | https://openalex.org/C127413603 |
| concepts[11].level | 0 |
| concepts[11].score | 0.16631674766540527 |
| concepts[11].wikidata | https://www.wikidata.org/wiki/Q11023 |
| concepts[11].display_name | Engineering |
| concepts[12].id | https://openalex.org/C33923547 |
| concepts[12].level | 0 |
| concepts[12].score | 0.14837118983268738 |
| concepts[12].wikidata | https://www.wikidata.org/wiki/Q395 |
| concepts[12].display_name | Mathematics |
| concepts[13].id | https://openalex.org/C94375191 |
| concepts[13].level | 1 |
| concepts[13].score | 0.0 |
| concepts[13].wikidata | https://www.wikidata.org/wiki/Q11205 |
| concepts[13].display_name | Arithmetic |
| keywords[0].id | https://openalex.org/keywords/xnor-gate |
| keywords[0].score | 0.8935666084289551 |
| keywords[0].display_name | XNOR gate |
| keywords[1].id | https://openalex.org/keywords/computer-science |
| keywords[1].score | 0.5862815976142883 |
| keywords[1].display_name | Computer science |
| keywords[2].id | https://openalex.org/keywords/encoding |
| keywords[2].score | 0.5504317879676819 |
| keywords[2].display_name | Encoding (memory) |
| keywords[3].id | https://openalex.org/keywords/binary-number |
| keywords[3].score | 0.4641405940055847 |
| keywords[3].display_name | Binary number |
| keywords[4].id | https://openalex.org/keywords/topology |
| keywords[4].score | 0.4235374331474304 |
| keywords[4].display_name | Topology (electrical circuits) |
| keywords[5].id | https://openalex.org/keywords/computer-hardware |
| keywords[5].score | 0.3665306270122528 |
| keywords[5].display_name | Computer hardware |
| keywords[6].id | https://openalex.org/keywords/logic-gate |
| keywords[6].score | 0.2605476379394531 |
| keywords[6].display_name | Logic gate |
| keywords[7].id | https://openalex.org/keywords/electrical-engineering |
| keywords[7].score | 0.21678516268730164 |
| keywords[7].display_name | Electrical engineering |
| keywords[8].id | https://openalex.org/keywords/artificial-intelligence |
| keywords[8].score | 0.19573771953582764 |
| keywords[8].display_name | Artificial intelligence |
| keywords[9].id | https://openalex.org/keywords/algorithm |
| keywords[9].score | 0.18437868356704712 |
| keywords[9].display_name | Algorithm |
| keywords[10].id | https://openalex.org/keywords/nand-gate |
| keywords[10].score | 0.17842474579811096 |
| keywords[10].display_name | NAND gate |
| keywords[11].id | https://openalex.org/keywords/engineering |
| keywords[11].score | 0.16631674766540527 |
| keywords[11].display_name | Engineering |
| keywords[12].id | https://openalex.org/keywords/mathematics |
| keywords[12].score | 0.14837118983268738 |
| keywords[12].display_name | Mathematics |
| language | en |
| locations[0].id | doi:10.1109/jxcdc.2023.3320677 |
| locations[0].is_oa | True |
| locations[0].source.id | https://openalex.org/S2478001734 |
| locations[0].source.issn | 2329-9231 |
| locations[0].source.type | journal |
| locations[0].source.is_oa | True |
| locations[0].source.issn_l | 2329-9231 |
| locations[0].source.is_core | True |
| locations[0].source.is_in_doaj | True |
| locations[0].source.display_name | IEEE Journal on Exploratory Solid-State Computational Devices and Circuits |
| locations[0].source.host_organization | https://openalex.org/P4310319808 |
| locations[0].source.host_organization_name | Institute of Electrical and Electronics Engineers |
| locations[0].source.host_organization_lineage | https://openalex.org/P4310319808 |
| locations[0].source.host_organization_lineage_names | Institute of Electrical and Electronics Engineers |
| locations[0].license | |
| locations[0].pdf_url | https://ieeexplore.ieee.org/ielx7/6570653/7076742/10268108.pdf |
| locations[0].version | publishedVersion |
| locations[0].raw_type | journal-article |
| locations[0].license_id | |
| locations[0].is_accepted | True |
| locations[0].is_published | True |
| locations[0].raw_source_name | IEEE Journal on Exploratory Solid-State Computational Devices and Circuits |
| locations[0].landing_page_url | https://doi.org/10.1109/jxcdc.2023.3320677 |
| locations[1].id | pmh:oai:doaj.org/article:330e2de940344536b49ad82d2339d95f |
| locations[1].is_oa | False |
| locations[1].source.id | https://openalex.org/S4306401280 |
| locations[1].source.issn | |
| locations[1].source.type | repository |
| locations[1].source.is_oa | False |
| locations[1].source.issn_l | |
| locations[1].source.is_core | False |
| locations[1].source.is_in_doaj | False |
| locations[1].source.display_name | DOAJ (DOAJ: Directory of Open Access Journals) |
| locations[1].source.host_organization | |
| locations[1].source.host_organization_name | |
| locations[1].license | |
| locations[1].pdf_url | |
| locations[1].version | submittedVersion |
| locations[1].raw_type | article |
| locations[1].license_id | |
| locations[1].is_accepted | False |
| locations[1].is_published | False |
| locations[1].raw_source_name | IEEE Journal on Exploratory Solid-State Computational Devices and Circuits, Vol 9, Iss 2, Pp 99-107 (2023) |
| locations[1].landing_page_url | https://doaj.org/article/330e2de940344536b49ad82d2339d95f |
| indexed_in | crossref, doaj |
| authorships[0].author.id | https://openalex.org/A5012075933 |
| authorships[0].author.orcid | https://orcid.org/0000-0003-4965-0533 |
| authorships[0].author.display_name | Karam Cho |
| authorships[0].countries | US |
| authorships[0].affiliations[0].institution_ids | https://openalex.org/I1343180700 |
| authorships[0].affiliations[0].raw_affiliation_string | Intel Corporation, Hillsboro, OR, USA |
| authorships[0].affiliations[1].institution_ids | https://openalex.org/I219193219 |
| authorships[0].affiliations[1].raw_affiliation_string | Elmore Family School of Electrical and Computer Engineering, Purdue University, West Lafayette, IN, USA |
| authorships[0].institutions[0].id | https://openalex.org/I1343180700 |
| authorships[0].institutions[0].ror | https://ror.org/01ek73717 |
| authorships[0].institutions[0].type | company |
| authorships[0].institutions[0].lineage | https://openalex.org/I1343180700 |
| authorships[0].institutions[0].country_code | US |
| authorships[0].institutions[0].display_name | Intel (United States) |
| authorships[0].institutions[1].id | https://openalex.org/I219193219 |
| authorships[0].institutions[1].ror | https://ror.org/02dqehb95 |
| authorships[0].institutions[1].type | education |
| authorships[0].institutions[1].lineage | https://openalex.org/I219193219 |
| authorships[0].institutions[1].country_code | US |
| authorships[0].institutions[1].display_name | Purdue University West Lafayette |
| authorships[0].author_position | first |
| authorships[0].raw_author_name | Karam Cho |
| authorships[0].is_corresponding | False |
| authorships[0].raw_affiliation_strings | Elmore Family School of Electrical and Computer Engineering, Purdue University, West Lafayette, IN, USA, Intel Corporation, Hillsboro, OR, USA |
| authorships[1].author.id | https://openalex.org/A5035901172 |
| authorships[1].author.orcid | https://orcid.org/0000-0002-6152-2377 |
| authorships[1].author.display_name | Akul Malhotra |
| authorships[1].countries | US |
| authorships[1].affiliations[0].institution_ids | https://openalex.org/I219193219 |
| authorships[1].affiliations[0].raw_affiliation_string | Elmore Family School of Electrical and Computer Engineering, Purdue University, West Lafayette, IN, USA |
| authorships[1].institutions[0].id | https://openalex.org/I219193219 |
| authorships[1].institutions[0].ror | https://ror.org/02dqehb95 |
| authorships[1].institutions[0].type | education |
| authorships[1].institutions[0].lineage | https://openalex.org/I219193219 |
| authorships[1].institutions[0].country_code | US |
| authorships[1].institutions[0].display_name | Purdue University West Lafayette |
| authorships[1].author_position | middle |
| authorships[1].raw_author_name | Akul Malhotra |
| authorships[1].is_corresponding | False |
| authorships[1].raw_affiliation_strings | Elmore Family School of Electrical and Computer Engineering, Purdue University, West Lafayette, IN, USA |
| authorships[2].author.id | https://openalex.org/A5044276472 |
| authorships[2].author.orcid | https://orcid.org/0000-0001-5609-9722 |
| authorships[2].author.display_name | Sumeet Kumar Gupta |
| authorships[2].countries | US |
| authorships[2].affiliations[0].institution_ids | https://openalex.org/I219193219 |
| authorships[2].affiliations[0].raw_affiliation_string | Elmore Family School of Electrical and Computer Engineering, Purdue University, West Lafayette, IN, USA |
| authorships[2].institutions[0].id | https://openalex.org/I219193219 |
| authorships[2].institutions[0].ror | https://ror.org/02dqehb95 |
| authorships[2].institutions[0].type | education |
| authorships[2].institutions[0].lineage | https://openalex.org/I219193219 |
| authorships[2].institutions[0].country_code | US |
| authorships[2].institutions[0].display_name | Purdue University West Lafayette |
| authorships[2].author_position | last |
| authorships[2].raw_author_name | Sumeet Kumar Gupta |
| authorships[2].is_corresponding | False |
| authorships[2].raw_affiliation_strings | Elmore Family School of Electrical and Computer Engineering, Purdue University, West Lafayette, IN, USA |
| has_content.pdf | True |
| has_content.grobid_xml | True |
| is_paratext | False |
| open_access.is_oa | True |
| open_access.oa_url | https://ieeexplore.ieee.org/ielx7/6570653/7076742/10268108.pdf |
| open_access.oa_status | gold |
| open_access.any_repository_has_fulltext | False |
| created_date | 2025-10-10T00:00:00 |
| display_name | XNOR-VSH: A Valley-Spin Hall Effect-Based Compact and Energy-Efficient Synaptic Crossbar Array for Binary Neural Networks |
| has_fulltext | True |
| is_retracted | False |
| updated_date | 2025-11-06T03:46:38.306776 |
| primary_topic.id | https://openalex.org/T10502 |
| primary_topic.field.id | https://openalex.org/fields/22 |
| primary_topic.field.display_name | Engineering |
| primary_topic.score | 1.0 |
| primary_topic.domain.id | https://openalex.org/domains/3 |
| primary_topic.domain.display_name | Physical Sciences |
| primary_topic.subfield.id | https://openalex.org/subfields/2208 |
| primary_topic.subfield.display_name | Electrical and Electronic Engineering |
| primary_topic.display_name | Advanced Memory and Neural Computing |
| related_works | https://openalex.org/W2108719777, https://openalex.org/W2910771446, https://openalex.org/W2966758645, https://openalex.org/W2122693377, https://openalex.org/W2559054477, https://openalex.org/W4320854861, https://openalex.org/W2763203754, https://openalex.org/W3048955117, https://openalex.org/W2532170798, https://openalex.org/W2166656370 |
| cited_by_count | 5 |
| counts_by_year[0].year | 2025 |
| counts_by_year[0].cited_by_count | 2 |
| counts_by_year[1].year | 2024 |
| counts_by_year[1].cited_by_count | 2 |
| counts_by_year[2].year | 2023 |
| counts_by_year[2].cited_by_count | 1 |
| locations_count | 2 |
| best_oa_location.id | doi:10.1109/jxcdc.2023.3320677 |
| best_oa_location.is_oa | True |
| best_oa_location.source.id | https://openalex.org/S2478001734 |
| best_oa_location.source.issn | 2329-9231 |
| best_oa_location.source.type | journal |
| best_oa_location.source.is_oa | True |
| best_oa_location.source.issn_l | 2329-9231 |
| best_oa_location.source.is_core | True |
| best_oa_location.source.is_in_doaj | True |
| best_oa_location.source.display_name | IEEE Journal on Exploratory Solid-State Computational Devices and Circuits |
| best_oa_location.source.host_organization | https://openalex.org/P4310319808 |
| best_oa_location.source.host_organization_name | Institute of Electrical and Electronics Engineers |
| best_oa_location.source.host_organization_lineage | https://openalex.org/P4310319808 |
| best_oa_location.source.host_organization_lineage_names | Institute of Electrical and Electronics Engineers |
| best_oa_location.license | |
| best_oa_location.pdf_url | https://ieeexplore.ieee.org/ielx7/6570653/7076742/10268108.pdf |
| best_oa_location.version | publishedVersion |
| best_oa_location.raw_type | journal-article |
| best_oa_location.license_id | |
| best_oa_location.is_accepted | True |
| best_oa_location.is_published | True |
| best_oa_location.raw_source_name | IEEE Journal on Exploratory Solid-State Computational Devices and Circuits |
| best_oa_location.landing_page_url | https://doi.org/10.1109/jxcdc.2023.3320677 |
| primary_location.id | doi:10.1109/jxcdc.2023.3320677 |
| primary_location.is_oa | True |
| primary_location.source.id | https://openalex.org/S2478001734 |
| primary_location.source.issn | 2329-9231 |
| primary_location.source.type | journal |
| primary_location.source.is_oa | True |
| primary_location.source.issn_l | 2329-9231 |
| primary_location.source.is_core | True |
| primary_location.source.is_in_doaj | True |
| primary_location.source.display_name | IEEE Journal on Exploratory Solid-State Computational Devices and Circuits |
| primary_location.source.host_organization | https://openalex.org/P4310319808 |
| primary_location.source.host_organization_name | Institute of Electrical and Electronics Engineers |
| primary_location.source.host_organization_lineage | https://openalex.org/P4310319808 |
| primary_location.source.host_organization_lineage_names | Institute of Electrical and Electronics Engineers |
| primary_location.license | |
| primary_location.pdf_url | https://ieeexplore.ieee.org/ielx7/6570653/7076742/10268108.pdf |
| primary_location.version | publishedVersion |
| primary_location.raw_type | journal-article |
| primary_location.license_id | |
| primary_location.is_accepted | True |
| primary_location.is_published | True |
| primary_location.raw_source_name | IEEE Journal on Exploratory Solid-State Computational Devices and Circuits |
| primary_location.landing_page_url | https://doi.org/10.1109/jxcdc.2023.3320677 |
| publication_date | 2023-09-29 |
| publication_year | 2023 |
| referenced_works | https://openalex.org/W3139521791, https://openalex.org/W2896122000, https://openalex.org/W3042468132, https://openalex.org/W3208067593, https://openalex.org/W2300242332, https://openalex.org/W3000301330, https://openalex.org/W2798554798, https://openalex.org/W4225755231, https://openalex.org/W4205230840, https://openalex.org/W3195413970, https://openalex.org/W2930624726, https://openalex.org/W3175040915, https://openalex.org/W3113114492, https://openalex.org/W2996305698, https://openalex.org/W2057701641, https://openalex.org/W2803975251, https://openalex.org/W3006802526, https://openalex.org/W4200419998, https://openalex.org/W2096445739, https://openalex.org/W2803325289, https://openalex.org/W3187831751, https://openalex.org/W3026337110, https://openalex.org/W4312121016, https://openalex.org/W4285588914, https://openalex.org/W3177592084, https://openalex.org/W2088797290, https://openalex.org/W2799745003, https://openalex.org/W3103565263 |
| referenced_works_count | 28 |
| abstract_inverted_index.a | 47, 64, 98 |
| abstract_inverted_index.In | 38 |
| abstract_inverted_index.We | 91, 160 |
| abstract_inverted_index.an | 6, 30, 80 |
| abstract_inverted_index.by | 45 |
| abstract_inverted_index.in | 63, 74, 171 |
| abstract_inverted_index.of | 55, 165 |
| abstract_inverted_index.on | 173 |
| abstract_inverted_index.or | 33 |
| abstract_inverted_index.to | 24, 29, 78, 101, 148 |
| abstract_inverted_index.we | 41 |
| abstract_inverted_index.IMC | 138 |
| abstract_inverted_index.Our | 67, 125 |
| abstract_inverted_index.VSH | 95 |
| abstract_inverted_index.and | 49, 88, 97, 112, 135, 140, 155, 168 |
| abstract_inverted_index.dot | 57, 105 |
| abstract_inverted_index.for | 9, 176 |
| abstract_inverted_index.low | 50 |
| abstract_inverted_index.the | 93, 129, 163, 177, 182 |
| abstract_inverted_index.two | 22 |
| abstract_inverted_index.(AI) | 14 |
| abstract_inverted_index.BNNs | 180 |
| abstract_inverted_index.Hall | 71 |
| abstract_inverted_index.XNOR | 81 |
| abstract_inverted_index.also | 161 |
| abstract_inverted_index.area | 31, 146 |
| abstract_inverted_index.edge | 11 |
| abstract_inverted_index.have | 4 |
| abstract_inverted_index.show | 127 |
| abstract_inverted_index.that | 128 |
| abstract_inverted_index.this | 39, 43 |
| abstract_inverted_index.with | 85, 116, 143 |
| abstract_inverted_index.~\mu | 122 |
| abstract_inverted_index.(IMC) | 54 |
| abstract_inverted_index.(VSH) | 72 |
| abstract_inverted_index.array | 100, 132 |
| abstract_inverted_index.based | 158 |
| abstract_inverted_index.issue | 44 |
| abstract_inverted_index.lower | 137 |
| abstract_inverted_index.power | 51 |
| abstract_inverted_index.prior | 17 |
| abstract_inverted_index.sense | 117 |
| abstract_inverted_index.shown | 5 |
| abstract_inverted_index.using | 181 |
| abstract_inverted_index.(BNNs) | 3 |
| abstract_inverted_index.(MRAM) | 154 |
| abstract_inverted_index.(named | 83 |
| abstract_inverted_index.Binary | 0 |
| abstract_inverted_index.access | 152 |
| abstract_inverted_index.binary | 110, 114 |
| abstract_inverted_index.design | 79 |
| abstract_inverted_index.device | 96 |
| abstract_inverted_index.effect | 73 |
| abstract_inverted_index.either | 20 |
| abstract_inverted_index.enable | 102 |
| abstract_inverted_index.encode | 25 |
| abstract_inverted_index.impact | 164 |
| abstract_inverted_index.inputs | 111 |
| abstract_inverted_index.margin | 118 |
| abstract_inverted_index.memory | 99, 153 |
| abstract_inverted_index.neural | 1 |
| abstract_inverted_index.random | 151 |
| abstract_inverted_index.robust | 103 |
| abstract_inverted_index.signed | 26, 60, 109, 113 |
| abstract_inverted_index.single | 65 |
| abstract_inverted_index.weight | 61 |
| abstract_inverted_index.address | 42 |
| abstract_inverted_index.between | 108 |
| abstract_inverted_index.compact | 48 |
| abstract_inverted_index.complex | 35 |
| abstract_inverted_index.designs | 18 |
| abstract_inverted_index.energy, | 141 |
| abstract_inverted_index.immense | 7 |
| abstract_inverted_index.latency | 139 |
| abstract_inverted_index.leading | 28 |
| abstract_inverted_index.present | 162 |
| abstract_inverted_index.process | 169 |
| abstract_inverted_index.product | 106 |
| abstract_inverted_index.promise | 8 |
| abstract_inverted_index.require | 21, 34 |
| abstract_inverted_index.results | 126 |
| abstract_inverted_index.smaller | 145 |
| abstract_inverted_index.storage | 87 |
| abstract_inverted_index.trained | 178 |
| abstract_inverted_index.weights | 27, 115 |
| abstract_inverted_index.CIFAR-10 | 183 |
| abstract_inverted_index.However, | 16 |
| abstract_inverted_index.XNOR-VSH | 131, 172 |
| abstract_inverted_index.accuracy | 175 |
| abstract_inverted_index.achieves | 133 |
| abstract_inverted_index.approach | 68 |
| abstract_inverted_index.article, | 40 |
| abstract_inverted_index.bit-cell | 82 |
| abstract_inverted_index.compared | 147 |
| abstract_inverted_index.dataset. | 184 |
| abstract_inverted_index.encoding | 62 |
| abstract_inverted_index.hardware | 166 |
| abstract_inverted_index.networks | 2 |
| abstract_inverted_index.products | 58 |
| abstract_inverted_index.proposed | 94, 130 |
| abstract_inverted_index.tungsten | 76 |
| abstract_inverted_index.utilizes | 69 |
| abstract_inverted_index.<tex-math | 120 |
| abstract_inverted_index.ResNet-18 | 179 |
| abstract_inverted_index.\text{A}$ | 123 |
| abstract_inverted_index.bit-cell. | 66 |
| abstract_inverted_index.bit-cells | 23 |
| abstract_inverted_index.computing | 53 |
| abstract_inverted_index.featuring | 59 |
| abstract_inverted_index.in-memory | 52, 104 |
| abstract_inverted_index.monolayer | 75 |
| abstract_inverted_index.overhead, | 32 |
| abstract_inverted_index.proposing | 46 |
| abstract_inverted_index.topology. | 90 |
| abstract_inverted_index.typically | 19 |
| abstract_inverted_index.(SOT)-MRAM | 157 |
| abstract_inverted_index.XNOR-based | 56 |
| abstract_inverted_index.artificial | 12 |
| abstract_inverted_index.circuitry. | 37 |
| abstract_inverted_index.peripheral | 36 |
| abstract_inverted_index.platforms. | 15 |
| abstract_inverted_index.variations | 170 |
| abstract_inverted_index.co-optimize | 92 |
| abstract_inverted_index.di-selenide | 77 |
| abstract_inverted_index.valley-spin | 70 |
| abstract_inverted_index.XNOR-arrays. | 159 |
| abstract_inverted_index.computations | 107 |
| abstract_inverted_index.differential | 86 |
| abstract_inverted_index.intelligence | 13 |
| abstract_inverted_index.system-level | 174 |
| abstract_inverted_index.respectively, | 142 |
| abstract_inverted_index.(STT)-magnetic | 150 |
| abstract_inverted_index.non-idealities | 167 |
| abstract_inverted_index.spin-orbit-torque | 156 |
| abstract_inverted_index.notation="LaTeX">$1 | 121 |
| abstract_inverted_index.(SM)<inline-formula> | 119 |
| abstract_inverted_index.resource-constrained | 10 |
| abstract_inverted_index.spin-transfer-torque | 149 |
| abstract_inverted_index.access-transistor-less | 89 |
| abstract_inverted_index.“XNOR-VSH”) | 84 |
| abstract_inverted_index.37%–63% | 136 |
| abstract_inverted_index.49%–64% | 144 |
| abstract_inverted_index.</tex-math></inline-formula>. | 124 |
| abstract_inverted_index.4.8%–9.0% | 134 |
| cited_by_percentile_year.max | 97 |
| cited_by_percentile_year.min | 89 |
| countries_distinct_count | 1 |
| institutions_distinct_count | 3 |
| citation_normalized_percentile.value | 0.72344251 |
| citation_normalized_percentile.is_in_top_1_percent | False |
| citation_normalized_percentile.is_in_top_10_percent | False |