Alberto García-Ortiz
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View article: Interleaving cortex-analog mixing improves deep non-negative matrix factorization networks
Interleaving cortex-analog mixing improves deep non-negative matrix factorization networks Open
Considering biological constraints in artificial neural networks has led to dramatic improvements in performance. Nevertheless, to date, the positivity of long-range signals in the cortex has not been shown to yield improvements. While Non…
View article: Recursive regulator: a deep-learning and real-time model adaptation strategy for nonlinear systems
Recursive regulator: a deep-learning and real-time model adaptation strategy for nonlinear systems Open
Adaptive modeling is imperative for analyzing nonlinear systems deployed in natural dynamic environments. It facilitates filtering, prediction, and automatic control of the target object in real time to respond to unpredictable and non-rep…
View article: Low-Rank Equilibrium Propagation: An Online Incremental Learning Architecture for Analog-Based Hardware Accelerators
Low-Rank Equilibrium Propagation: An Online Incremental Learning Architecture for Analog-Based Hardware Accelerators Open
International audience
View article: VUSA: Virtually Upscaled Systolic Array Architecture to Exploit Unstructured Sparsity in AI Acceleration
VUSA: Virtually Upscaled Systolic Array Architecture to Exploit Unstructured Sparsity in AI Acceleration Open
Leveraging high degrees of unstructured sparsity is a promising approach to enhance the efficiency of deep neural network DNN accelerators - particularly important for emerging Edge-AI applications. We introduce VUSA, a systolic-array arch…
View article: ELSE: Efficient Deep Neural Network Inference Through Line-Based Sparsity Exploration
ELSE: Efficient Deep Neural Network Inference Through Line-Based Sparsity Exploration Open
Brain-inspired computer architecture facilitates low-power, low-latency deep neural network inference for embedded AI applications. The hardware performance crucially hinges on the quantity of non-zero activations (i.e., events) during inf…
View article: Exploiting Neural-Network Statistics for Low-Power DNN Inference
Exploiting Neural-Network Statistics for Low-Power DNN Inference Open
Specialized compute blocks have been developed for efficient nn execution. However, due to the vast amount of data and parameter movements, the interconnects and on-chip memories form another bottleneck, impairing power and performance. Th…
View article: Exploiting Neural-Network Statistics for Low-Power DNN Inference
Exploiting Neural-Network Statistics for Low-Power DNN Inference Open
Specialized compute blocks have been developed for efficient DNN execution. However, due to the vast amount of data and parameter movements, the interconnects and on-chip memories form another bottleneck, impairing power and performance. T…
View article: Competitive performance and superior noise robustness of a non-negative deep convolutional spiking network
Competitive performance and superior noise robustness of a non-negative deep convolutional spiking network Open
Networks of spiking neurons promise to combine energy efficiency with high performance. However, spiking models that match the performance of current state-of-the-art networks while requiring moderate computational resources are still lack…
View article: Energy-based analog neural network framework
Energy-based analog neural network framework Open
Over the past decade a body of work has emerged and shown the disruptive potential of neuromorphic systems across a broad range of studies, often combining novel machine learning models and nanotechnologies. Still, the scope of investigati…
View article: CNN Sensor Analytics With Hybrid-Float6 Quantization on Low-Power Embedded FPGAs
CNN Sensor Analytics With Hybrid-Float6 Quantization on Low-Power Embedded FPGAs Open
The use of artificial intelligence (AI) in sensor analytics is entering a new era based on the use of ubiquitous embedded connected devices. This transformation requires the adoption of design techniques that reconcile accurate results wit…
View article: Energy-Based Analog Neural Network Framework
Energy-Based Analog Neural Network Framework Open
International audience
View article: Hier-3D: A Hierarchical Physical Design Methodology for Face-to-Face-Bonded 3D ICs
Hier-3D: A Hierarchical Physical Design Methodology for Face-to-Face-Bonded 3D ICs Open
Hierarchical very-large-scale integration (VLSI) flows are an understudied yet critical approach to achieving design closure at giga-scale complexity and gigahertz frequency targets. This paper proposes a novel hierarchical physical design…
View article: MemPool-3D: Boosting Performance and Efficiency of Shared-L1 Memory Many-Core Clusters with 3D Integration
MemPool-3D: Boosting Performance and Efficiency of Shared-L1 Memory Many-Core Clusters with 3D Integration Open
Three-dimensional integrated circuits promise power, performance, and\nfootprint gains compared to their 2D counterparts, thanks to drastic reductions\nin the interconnects' length through their smaller form factor. We can leverage\nthe po…
View article: Implications of Non-Uniform Deadline Scaling to Quality of Service Under Single Errors
Implications of Non-Uniform Deadline Scaling to Quality of Service Under Single Errors Open
Fault-tolerant real-time systems for emerging critical applications like wearable electronic healthcare monitors, consumer-grade unmanned aerial vehicles, or environmental monitoring have to tolerate errors during operation. If they fail, …
View article: MemPool-3D: Boosting Performance and Efficiency of Shared-L1 Memory Many-Core Clusters with 3D Integration
MemPool-3D: Boosting Performance and Efficiency of Shared-L1 Memory Many-Core Clusters with 3D Integration Open
Three-dimensional integrated circuits promise power, performance, and footprint gains compared to their 2D counterparts, thanks to drastic reductions in the interconnects' length through their smaller form factor. We can leverage the poten…
View article: Power, Performance, Area and Cost Analysis of Memory-on-Logic Face-to-Face Bonded 3D Processor Designs
Power, Performance, Area and Cost Analysis of Memory-on-Logic Face-to-Face Bonded 3D Processor Designs Open
In this paper, we present a power, performance, area and cost (PPAC) analysis for large-scale 3D processor designs based on wafer-to-wafer bonding. From the evaluation of our cost model, we investigate a typically disregarded opportunity i…
View article: High-Performance Logic-on-Memory Monolithic 3-D IC Designs for Arm Cortex-A Processors
High-Performance Logic-on-Memory Monolithic 3-D IC Designs for Arm Cortex-A Processors Open
Monolithic 3-D IC (M3-D) is a promising solution to improve the performance and energy-efficiency of modern processors. But, designers are faced with challenges in design tools and methodologies, especially for power and thermal verificati…
View article: Accelerating Spike-by-Spike Neural Networks on FPGA With Hybrid Custom Floating-Point and Logarithmic Dot-Product Approximation
Accelerating Spike-by-Spike Neural Networks on FPGA With Hybrid Custom Floating-Point and Logarithmic Dot-Product Approximation Open
Spiking neural networks (SNNs) represent a promising alternative to conventional neural networks. In particular, the so-called Spike-by-Spike (SbS) neural networks provide exceptional noise robustness and reduced complexity. However, deep …
View article: Service Improvements in Real-Time Uniprocessor Scheduling With Single Errors
Service Improvements in Real-Time Uniprocessor Scheduling With Single Errors Open
Mixed-criticality scheduling in modern deeply embedded mission and safety-critical systems needs to consider delivered service, that is, the runtime in low criticality mode. If the change into a higher criticality mode is triggered by the …
View article: Combination of Task Allocation and Approximate Computing for Fog-Architecture-Based IoT
Combination of Task Allocation and Approximate Computing for Fog-Architecture-Based IoT Open
Achieving energy efficiency is always a primary concern for fog-architecture-based Internet of Things (IoT) applications. As the IoT devices are typically of small sizes and powered by battery energy, it is essential to address the energy …
View article: High Level Estimation of Power Consumption in Point-to-Point Interconnect Architectures
High Level Estimation of Power Consumption in Point-to-Point Interconnect Architectures Open
As technology shrinks, the importance of the communication architecture in the overall system performance and power consumption increases dramatically. In this work, a framework is developed to estimate the consumption in point-to-point in…
View article: SATA: An Intelligent Security Aware Task Allocation for Multihop Wireless Networks
SATA: An Intelligent Security Aware Task Allocation for Multihop Wireless Networks Open
Multihop wireless networks, which consist of sets of battery powered wireless nodes, have been widely spreading in numerous IoT applications. As the nodes typically have limited resources, many energy aware task allocation schemes are cond…
View article: Heterogeneous 3D Integration for a RISC-V System With STT-MRAM
Heterogeneous 3D Integration for a RISC-V System With STT-MRAM Open
Spin Torque Transfer Magnetic RAM (STT-MRAM) is a promising Non-Volatile Memory (NVM) technology achieving high density, low leakage power, and relatively small read/write delays. It provides a solution to improve the performance and to mi…
View article: Ratatoskr: An open-source framework for in-depth power, performance and area analysis in 3D NoCs
Ratatoskr: An open-source framework for in-depth power, performance and area analysis in 3D NoCs Open
We introduce ratatoskr, an open-source framework for in-depth power, performance and area (PPA) analysis in NoCs for 3D-integrated and heterogeneous System-on-Chips (SoCs). It covers all layers of abstraction by providing a NoC hardware im…
View article: System-Level Optimization of Network-on-Chips for Heterogeneous 3D System-on-Chips
System-Level Optimization of Network-on-Chips for Heterogeneous 3D System-on-Chips Open
For a system-level design of Networks-on-Chip for 3D heterogeneous System-on-Chip (SoC), the locations of components, routers and vertical links are determined from an application model and technology parameters. In conventional methods, t…