Alessandro Tempia Calvino
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View article: Back-end-aware Fault-tolerant Quantum Oracle Synthesis
Back-end-aware Fault-tolerant Quantum Oracle Synthesis Open
Quantum oracle synthesis involves compiling arbitrary Boolean functions into quantum circuits using specific quantum gates supported by the target quantum computer. The Clifford+T gate library is particularly common in fault-tolerant quant…
View article: Enhancing Delay-Driven LUT Mapping With Boolean Decomposition
Enhancing Delay-Driven LUT Mapping With Boolean Decomposition Open
Ashenhurst-Curtis decomposition (ACD) is a decomposition technique used, in particular, to map combinational logic into lookup tables (LUTs) structures when synthesizing hardware designs. However, available implementations of ACD suffer fr…
View article: Technology Legalization and Optimization for Adiabatic Quantum-Flux Parametron
Technology Legalization and Optimization for Adiabatic Quantum-Flux Parametron Open
Adiabatic quantum-flux parametron (AQFP) is an energy-efficient superconducting technology. Before physical design can be performed, AQFP technology mapping involves not only mapping logic into supported gate types but also legalizing the …
View article: Practical Boolean Decomposition for Delay-driven LUT Mapping
Practical Boolean Decomposition for Delay-driven LUT Mapping Open
Ashenhurst-Curtis decomposition (ACD) is a decomposition technique used, in particular, to map combinational logic into lookup tables (LUTs) structures when synthesizing hardware designs. However, available implementations of ACD suffer fr…
View article: Scalable Logic Rewriting Using Don't Cares
Scalable Logic Rewriting Using Don't Cares Open
Logic rewriting is a powerful optimization technique that replaces small sections of a Boolean network with better implementations. Typically, exact synthesis is used to compute optimum replacement on-the-fly, with possible support for Boo…
View article: Algebraic and Boolean Methods for SFQ Superconducting Circuits
Algebraic and Boolean Methods for SFQ Superconducting Circuits Open
Rapid single-flux quantum (RSFQ) is one of the most advanced and promising superconducting logic families, offering exceptional energy efficiency and speed. RSFQ technology requires delay registers (DFFs) and splitter cells to satisfy the …
View article: In Medio Stat Virtus*: Combining Boolean and Pattern Matching
In Medio Stat Virtus*: Combining Boolean and Pattern Matching Open
Technology mapping transforms a technology-independent representation into a technology-dependent one given a library of cells. This process is performed by means of local replacements that are extracted by matching sections of the subject…
View article: On the Synthesis of High-performance Homomorphic Boolean Circuits
On the Synthesis of High-performance Homomorphic Boolean Circuits Open
The rapid growth of cloud computing has intensified the need for secure data outsourcing solutions. Fully homomorphic encryption (FHE) offers a promising approach by enabling computations on encrypted data without exposing the plaintext. T…
View article: Technology Mapping Using Multi-Output Library Cells
Technology Mapping Using Multi-Output Library Cells Open
Technology mapping transforms a technology-independent representation into a technology-dependent one given a library of cells. Even if technology libraries contain multi-output cells, state-of-the-art techniques fully exploit single-outpu…
View article: Synthesis of SFQ Circuits with Compound Gates
Synthesis of SFQ Circuits with Compound Gates Open
Rapid single-flux quantum (RSFQ) is one of the most advanced superconducting technologies with the potential to supplement or replace conventional VLSI systems. However, scaling RSFQ systems up to VLSI complexity is challenging due to fund…
View article: Improving Standard-Cell Design Flow using Factored Form Optimization
Improving Standard-Cell Design Flow using Factored Form Optimization Open
Factored form is a powerful multi-level representa- tion of a Boolean function that readily translates into an imple- mentation of the function in CMOS technology. In particular, the number of literals in a factored form correlates strongl…
View article: Depth-Optimal Buffer and Splitter Insertion and Optimization in AQFP Circuits
Depth-Optimal Buffer and Splitter Insertion and Optimization in AQFP Circuits Open
The Adiabatic Quantum-Flux Parametron (AQFP) is an energy-efficient superconducting logic family. AQFP technology requires buffer and splitting elements (B/S) to be inserted to satisfy path-balancing and fanout-branching constraints. B/S i…
View article: Utilizing XMG-Based Synthesis to Preserve Self-Duality for RFET-Based Circuits
Utilizing XMG-Based Synthesis to Preserve Self-Duality for RFET-Based Circuits Open
In the last few decades, two major phenomena have revolutionized the electronic industry – the ever-increasing dependence on electronic circuits and the Complementary Metal Oxide Semiconductor (CMOS) downscaling. These two phenomena have b…
View article: Majority-based Design Flow for AQFP Superconducting Family
Majority-based Design Flow for AQFP Superconducting Family Open
Adiabatic superconducting devices are promising candidates to develop high-speed/low-power electronics. Advances in physical technology must be matched with a systematic development of comprehensive design and simulation tools to bring sup…
View article: A Versatile Mapping Approach for Technology Mapping and Graph Optimization
A Versatile Mapping Approach for Technology Mapping and Graph Optimization Open
This paper proposes a versatile mapping approach that has three objectives: i) it can map from one technology-independent graph representation to another; ii) it can map to a cell library; iii) it supports logic rewriting. The method is cu…
View article: SysML Models Verification Relying on Dependency Graphs
SysML Models Verification Relying on Dependency Graphs Open
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View article: Direct Model-checking of SysML Models
Direct Model-checking of SysML Models Open
Model-checking intends to verify whether a property is satisfied by a model, or not. Model-checking of high-level models, e.g. SysML models, usually first requires a model transformation to a low level formal specification. The present pap…