Ali Akoglu
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View article: HOPPERFISH: Holistic Profiling with Portable Extensible and Robust Framework Intended for Systems with Heterogeneity
HOPPERFISH: Holistic Profiling with Portable Extensible and Robust Framework Intended for Systems with Heterogeneity Open
We introduce HOPPERFISH , a holistic profiling framework that unifies analysis across the application, runtime, microarchitecture, and hardware layers to streamline robust feature correlation in heterogeneous computing systems. HOPPERFISH …
View article: RIMMS: Runtime Integrated Memory Management System for Heterogeneous Computing
RIMMS: Runtime Integrated Memory Management System for Heterogeneous Computing Open
Efficient memory management in heterogeneous systems is increasingly challenging due to diverse compute architectures (e.g., CPU, GPU, and FPGA) and dynamic task mappings not known at compile time. Existing approaches often require program…
View article: RIMMS: Runtime Integrated Memory Management System for Heterogeneous Computing
RIMMS: Runtime Integrated Memory Management System for Heterogeneous Computing Open
Efficient memory management in heterogeneous systems is increasingly challenging due to diverse compute architectures (e.g., CPU, GPU, FPGA) and dynamic task mappings not known at compile time. Existing approaches often require programmers…
View article: Compilation Framework for Dynamically Reconfigurable Array Architectures
Compilation Framework for Dynamically Reconfigurable Array Architectures Open
This paper presents a compilation and scheduling framework for high-performance mapping of computationally-intensive kernels on Dynamically Reconfigurable Array Architectures. We showcase the framework for Domain Adaptive Processor (DAP) -…
View article: Coarse-Grained Task Parallelization by Dynamic Profiling for Heterogeneous SoC-Based Embedded System
Coarse-Grained Task Parallelization by Dynamic Profiling for Heterogeneous SoC-Based Embedded System Open
In this study, we introduce a methodology for automatically transforming user applications written in C/C++ to a parallel representation consisting of coarse-grained tasks based on dynamic profiling. Such a parallel representation is suita…
View article: Tutorial: A Novel Runtime Environment for Accelerator-Rich Heterogeneous Architectures
Tutorial: A Novel Runtime Environment for Accelerator-Rich Heterogeneous Architectures Open
As the landscape of computing advances, system designers are increasingly exploring methodologies that leverage higher levels of heterogeneity to enhance performance within constrained size, weight, power, and cost parameters. CEDR (Compil…
View article: GPU-RANC: A CUDA Accelerated Simulation Framework for Neuromorphic Architectures
GPU-RANC: A CUDA Accelerated Simulation Framework for Neuromorphic Architectures Open
Open-source simulation tools play a crucial role for neuromorphic application engineers and hardware architects to investigate performance bottlenecks and explore design optimizations before committing to silicon. Reconfigurable Architectu…
View article: PyTorch and CEDR: Enabling Deployment of Machine Learning Models on Heterogeneous Computing Systems
PyTorch and CEDR: Enabling Deployment of Machine Learning Models on Heterogeneous Computing Systems Open
The PyTorch programming interface enables efficient deployment of machine learning models, leveraging the parallelism offered by GPU architectures. In this study, we present the integration of the PyTorch framework with a compiler and runt…
View article: Value-Based Resource Management at SoC Scale
Value-Based Resource Management at SoC Scale Open
Value-based resource management heuristics, which are traditionally deployed in heterogeneous HPC systems, maximize system productivity by assigning resources to each job based on its priority and estimated value gain relative to each job'…
View article: Theoretical Validation and Hardware Implementation of Dynamic Adaptive Scheduling for Heterogeneous Systems on Chip
Theoretical Validation and Hardware Implementation of Dynamic Adaptive Scheduling for Heterogeneous Systems on Chip Open
Domain-specific systems on chip (DSSoCs) aim to narrow the gap between general-purpose processors and application-specific designs. CPU clusters enable programmability, whereas hardware accelerators tailored to the target domain minimize t…
View article: Theoretical Validation and Hardware Implementation of Dynamic Adaptive Scheduling for Heterogeneous Systems-on-Chip
Theoretical Validation and Hardware Implementation of Dynamic Adaptive Scheduling for Heterogeneous Systems-on-Chip Open
Domain-specific systems-on-chip (DSSoCs) aim to narrow the gap between general-purpose processors and application-specific designs. CPU clusters enable programmability, while hardware accelerators tailored to the target domain minimize tas…
View article: Contention-aware Performance Modeling for Heterogeneous Edge and Cloud Systems
Contention-aware Performance Modeling for Heterogeneous Edge and Cloud Systems Open
Diversely Heterogeneous System-on-Chips (DH-SoC) are increasingly popular computing platforms in many fields, such as autonomous driving and AR/VR applications, due to their ability to effectively balance performance and energy efficiency.…
View article: GPU-based and Streaming-enabled Implementation of Pre-processing Flow towards Enhancing Optical Character Recognition Accuracy and Efficiency
GPU-based and Streaming-enabled Implementation of Pre-processing Flow towards Enhancing Optical Character Recognition Accuracy and Efficiency Open
Research has demonstrated that digital images can be pre-processed through operations such as scaling, rotation, and blurring to enhance the accuracy of optical character recognition (OCR) by emphasizing important features within the image…
View article: A Novel Implementation Methodology for Error Correction Codes on a Neuromorphic Architecture
A Novel Implementation Methodology for Error Correction Codes on a Neuromorphic Architecture Open
The Internet of Things infrastructure connects a massive number of edge devices with an increasing demand for intelligent sensing and inferencing capability. Such data-sensitive functions necessitate energy-efficient and programmable imple…
View article: A Novel Implementation Methodology for Error Correction Codes on a Neuromorphic Architecture
A Novel Implementation Methodology for Error Correction Codes on a Neuromorphic Architecture Open
The Internet of Things infrastructure connects a massive number of edge devices with an increasing demand for intelligent sensing and inferencing capability. Such data-sensitive functions necessitate energy-efficient and programmable imple…
View article: CEDR-API: Productive, Performant Programming of Domain-Specific Embedded Systems
CEDR-API: Productive, Performant Programming of Domain-Specific Embedded Systems Open
As the computing landscape evolves, system designers continue to explore design methodologies that leverage increased levels of heterogeneity to push performance within limited size, weight, power, and cost budgets. One such methodology is…
View article: Profile-Guided Parallel Task Extraction and Execution for Domain Specific Heterogeneous SoC
Profile-Guided Parallel Task Extraction and Execution for Domain Specific Heterogeneous SoC Open
In this study, we introduce a methodology for automatically transforming user applications in the radar and communication domain written in C/C++ based on dynamic profiling to a parallel representation targeted for a heterogeneous SoC. We …
View article: Graph analytics workflows enactment on just in time data centres, Position Paper
Graph analytics workflows enactment on just in time data centres, Position Paper Open
This paper discusses our vision of multirole-capable decision-making systems across a broad range of Data Science (DS) workflows working on graphs through disaggregated data centres. Our vision is that an alternative is possible to work on…
View article: A Hardware-based HEFT Scheduler Implementation for Dynamic Workloads on Heterogeneous SoCs
A Hardware-based HEFT Scheduler Implementation for Dynamic Workloads on Heterogeneous SoCs Open
Non-uniform performance and power consumption across the processing elements (PEs) of heterogeneous SoCs increase the computation complexity of the task scheduling problem compared to homogeneous architectures. Latency of a software-based …
View article: CEDR: A Compiler-integrated, Extensible DSSoC Runtime
CEDR: A Compiler-integrated, Extensible DSSoC Runtime Open
In this work, we present a C ompiler-integrated, E xtensible D omain Specific System on Chip R untime (CEDR) ecosystem to facilitate research toward addressing the challenges of architecture, system software, and application development wi…
View article: Performant, Multi-objective Scheduling of Highly Interleaved Task Graphs on Heterogeneous System on Chip Devices
Performant, Multi-objective Scheduling of Highly Interleaved Task Graphs on Heterogeneous System on Chip Devices Open
Performance-, power-, and energy-aware scheduling techniques play an essential role in optimally utilizing processing elements (PEs) of heterogeneous systems. List schedulers, a class of low-complexity static schedulers, have commonly been…
View article: JITA4DS: Disaggregated Execution of Data Science Pipelines Between the Edge and the Data Centre
JITA4DS: Disaggregated Execution of Data Science Pipelines Between the Edge and the Data Centre Open
This paper targets the execution of data science (DS) pipelines supported by data processing, transmission and sharing across several resources executing greedy processes. Current data science pipelines environments provide various infrast…
View article: DAS: Dynamic Adaptive Scheduling for Energy-Efficient Heterogeneous SoCs
DAS: Dynamic Adaptive Scheduling for Energy-Efficient Heterogeneous SoCs Open
Domain-specific systems-on-chip (DSSoCs) aim at bridging the gap between\napplication-specific integrated circuits (ASICs) and general-purpose\nprocessors. Traditional operating system (OS) schedulers can undermine the\npotential of DSSoCs…
View article: RANC: Reconfigurable Architecture for Neuromorphic Computing
RANC: Reconfigurable Architecture for Neuromorphic Computing Open
Neuromorphic architectures have been introduced as platforms for energy\nefficient spiking neural network execution. The massive parallelism offered by\nthese architectures has also triggered interest from non-machine learning\napplication…