André Seznec
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View article: TAGE: an engineering cookbook
TAGE: an engineering cookbook Open
CBP2016 TAGE-SC-L is generally considered as the state-of-the-art of branch predictors that have been been proposed in the academic world. This proposition suffers from several drawbacks, that forbids its direct implementation in hardware.…
View article: PDIP: Priority Directed Instruction Prefetching
PDIP: Priority Directed Instruction Prefetching Open
Modern server workloads have large code footprints which are prone to front-end bottlenecks due to instruction cache capacity misses. Even with the aggressive fetch directed instruction prefetching (FDIP), implemented in modern processors,…
View article: Conciliating Speed and Efficiency on Cache Compressors
Conciliating Speed and Efficiency on Cache Compressors Open
International audience
View article: A Case for Partial Co-Allocation Constraints in Compressed Caches
A Case for Partial Co-Allocation Constraints in Compressed Caches Open
Virtual Conference
View article: Understanding Cache Compression
Understanding Cache Compression Open
Hardware cache compression derives from software-compression research; yet, its implementation is not a straightforward translation, since it must abide by multiple restrictions to comply with area, power, and latency constraints. This stu…
View article: Leveraging Value Equality Prediction for Value Speculation
Leveraging Value Equality Prediction for Value Speculation Open
Value Prediction (VP) has recently been gaining interest in the research community, since prior work has established practical solutions for its implementation that provide meaningful performance gains. A constant challenge of contemporary…
View article: Compressed cache layout aware prefetching
Compressed cache layout aware prefetching Open
International audience
View article: The FNL+MMA Instruction Cache Prefetcher
The FNL+MMA Instruction Cache Prefetcher Open
International audience
View article: SIMT-X
SIMT-X Open
This work introduces Single Instruction Multi-Thread Express (SIMT-X), a general-purpose Central Processing Unit (CPU) microarchitecture that enables Graphics Processing Units (GPUs)-style SIMT execution across multiple threads of the same…
View article: Exploring value prediction limits
Exploring value prediction limits Open
International audience
View article: Value Speculation through Equality Prediction
Value Speculation through Equality Prediction Open
International audience
View article: Compressed Cache Layout Aware Prefetching
Compressed Cache Layout Aware Prefetching Open
The speed gap between CPU and memory is impairing performance. Cache compression and hardware prefetching are two techniques that could confront this bottleneck by decreasing last level cache misses. However, compression and prefetching ha…
View article: Synergistic cache layout for reuse and compression
Synergistic cache layout for reuse and compression Open
International audience
View article: Cost effective speculation with the omnipredictor
Cost effective speculation with the omnipredictor Open
International audience
View article: Exploring value prediction with the EVES predictor
Exploring value prediction with the EVES predictor Open
International audience
View article: On the Interactions Between Value Prediction and Compiler Optimizations in the Context of EOLE
On the Interactions Between Value Prediction and Compiler Optimizations in the Context of EOLE Open
Increasing instruction-level parallelism is regaining attractiveness within the microprocessor industry. The {Early | Out-of-order | Late} Execution (EOLE) microarchitecture and Differential Value TAgged GEometric (D-VTAGE) value predictor…
View article: Band-Pass Prefetching
Band-Pass Prefetching Open
In multi-core systems, an application’s prefetcher can interfere with the memory requests of other applications using the shared resources, such as last level cache and memory bandwidth. In order to minimize prefetcher-caused interference,…
View article: A Band-pass Prefetching : An Effective Prefetch Management Mechanism using Prefetch-fraction Metric in Multi-core Systems
A Band-pass Prefetching : An Effective Prefetch Management Mechanism using Prefetch-fraction Metric in Multi-core Systems Open
International audience
View article: On the Interactions Between Value Prediction and Compiler Optimizations in the Context of EOLE
On the Interactions Between Value Prediction and Compiler Optimizations in the Context of EOLE Open
International audience
View article: Compile-Time Function Memoization
Compile-Time Function Memoization Open
International audience
View article: Transforming TLP into DLP with the dynamic inter-thread vectorization architecture
Transforming TLP into DLP with the dynamic inter-thread vectorization architecture Open
Threads of Single-Program Multiple-Data (SPMD) applications often execute the same instructions on different data. We propose the Dynamic Inter-Thread Vectorization Architecture (DITVA) to leverage this implicit Data Level Parallelism in S…
View article: Storage-Free Memory Dependency Prediction
Storage-Free Memory Dependency Prediction Open
International audience
View article: Dynamic Inter-Thread Vectorization Architecture: extracting DLP from TLP
Dynamic Inter-Thread Vectorization Architecture: extracting DLP from TLP Open
International audience
View article: BADCO: behavioral application-dependent superscalar core model
BADCO: behavioral application-dependent superscalar core model Open
HAL is a multi-disciplinary open access archive for the deposit and dissemination of sci-entific research documents, whether they are pub-lished or not. The documents may come from teaching and research institutions in France or abroad, or…
View article: Service Value Aware Memory Scheduler by Estimating Request Weight and Using per-Thread Traffic Lights
Service Value Aware Memory Scheduler by Estimating Request Weight and Using per-Thread Traffic Lights Open
HAL is a multi-disciplinary open access archive for the deposit and dissemination of sci-entific research documents, whether they are pub-lished or not. The documents may come from teaching and research institutions in France or abroad, or…
View article: Dictionary Sharing: An Efficient Cache Compression Scheme for Compressed Caches
Dictionary Sharing: An Efficient Cache Compression Scheme for Compressed Caches Open
International audience
View article: Register sharing for equality prediction
Register sharing for equality prediction Open
International audience
View article: Yet Another Compressed Cache
Yet Another Compressed Cache Open
Cache memories play a critical role in bridging the latency, bandwidth, and energy gaps between cores and off-chip memory. However, caches frequently consume a significant fraction of a multicore chip's area and thus account for a signific…