Bangan Liu
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View article: NLJM: A Simplified Jitter Model of Digital Standard Cells for Rapid Automatic Design of Frequency Synthesizers
NLJM: A Simplified Jitter Model of Digital Standard Cells for Rapid Automatic Design of Frequency Synthesizers Open
Synthesizable frequency synthesizers implemented with digital standard cells and automatic layout synthesis have demonstrated significant potential in recent studies. However, synthesizing analog mixed-signal circuits still involves manual…
View article: A DPD/Dither-Free DPLL Based on a Cascaded Fractional Divider and Pseudo-Differential DTCs Achieving a —62.1-dBc Fractional Spur
A DPD/Dither-Free DPLL Based on a Cascaded Fractional Divider and Pseudo-Differential DTCs Achieving a —62.1-dBc Fractional Spur Open
View article: A synthesizable spread spectrum clock generator based on type-II/III fractional-<i>N</i> DPLL
A synthesizable spread spectrum clock generator based on type-II/III fractional-<i>N</i> DPLL Open
View article: A 6.5-to-8-GHz Cascaded Dual-Fractional- <i>N</i> Digital PLL Achieving −52.79-dBc Fractional Spur With 50-MHz Reference
A 6.5-to-8-GHz Cascaded Dual-Fractional- <i>N</i> Digital PLL Achieving −52.79-dBc Fractional Spur With 50-MHz Reference Open
View article: A Time-Mode-Modulation Digital Quadrature Power Amplifier Based on 1-bit Delta–Sigma Modulator and Hybrid FIR Filter
A Time-Mode-Modulation Digital Quadrature Power Amplifier Based on 1-bit Delta–Sigma Modulator and Hybrid FIR Filter Open
This article proposes a time-mode-modulation (TMM) digital quadrature power amplifier (PA), which can realize high power efficiency at power back-off (PBO) by applying the 1-bit delta-sigma modulator (DSM) and hybrid finite impulse respons…
View article: A Fully Synthesizable Fractional-<i>N</i> MDLL With Energy-Efficient Ring-Oscillator-Based DTC of Large Tuning Range
A Fully Synthesizable Fractional-<i>N</i> MDLL With Energy-Efficient Ring-Oscillator-Based DTC of Large Tuning Range Open
This letter describes a fully synthesizable fractional-N multiplexing delay-locked loop (MDLL) with a ring-oscillator-based digital-to-time converter (RO-DTC). The proposed RO-DTC can generate a wide range of time delays with only a relati…
View article: A low-power digital baseband circuit for GMSK demodulation in sub-GHz application
A low-power digital baseband circuit for GMSK demodulation in sub-GHz application Open
This paper proposed a digital synthesizable GMSK receiver baseband circuit for the Sub-GHz transceiver. The proposed digital baseband(DBB) circuit is composed of carrier recover, timing recovery, and demodulation blocks. An improved polari…
View article: A 32-kHz-Reference 2.4-GHz Fractional-<i>N</i> Oversampling PLL With 200-kHz Loop Bandwidth
A 32-kHz-Reference 2.4-GHz Fractional-<i>N</i> Oversampling PLL With 200-kHz Loop Bandwidth Open
In this article, a mixed–signal, 32-kHz reference-based 2.4-GHz fractional- over-sampling phase-locked loop (OSPLL) is proposed. Different from the conventional sampling PLL, which only uses zero-crossing timing information of the refere…
View article: A <i>Ka</i>-Band SATCOM Transceiver in 65-nm CMOS With High-Linearity TX and Dual-Channel Wide-Dynamic-Range RX for Terrestrial Terminal
A <i>Ka</i>-Band SATCOM Transceiver in 65-nm CMOS With High-Linearity TX and Dual-Channel Wide-Dynamic-Range RX for Terrestrial Terminal Open
In this article, a -band satellite communication (SATCOM) transceiver is first presented using a standard CMOS technology. The proposed -band SATCOM transceiver consists of a high-linearity transmitter (TX) and dual-channel receiver (RX)…
View article: A CMOS Dual-Polarized Phased-Array Beamformer Utilizing Cross-Polarization Leakage Cancellation for 5G MIMO Systems
A CMOS Dual-Polarized Phased-Array Beamformer Utilizing Cross-Polarization Leakage Cancellation for 5G MIMO Systems Open
This article introduces a power-efficient and low-cost CMOS 28-GHz phased-array beamformer supporting fifth-generation (5G) dual-polarized multiple-in-multiple-out (MIMO) (DP-MIMO) operation. To improve the cross-polarization (cross-pol.) …
View article: A Fully Synthesizable Fractional-<i>N</i> MDLL With Zero-Order Interpolation-Based DTC Nonlinearity Calibration and Two-Step Hybrid Phase Offset Calibration
A Fully Synthesizable Fractional-<i>N</i> MDLL With Zero-Order Interpolation-Based DTC Nonlinearity Calibration and Two-Step Hybrid Phase Offset Calibration Open
In this paper, a fully-synthesizable digital-to-time (DTC)-based fractional-N multiplying delay-locked loop,(MDLL) is presented. Noise and linearity of synthesizable DTCs are analyzed, and a two-stage synthesizable DTC is proposed in which…
View article: A 28-GHz CMOS Phased-Array Beamformer Utilizing Neutralized Bi-Directional Technique Supporting Dual-Polarized MIMO for 5G NR
A 28-GHz CMOS Phased-Array Beamformer Utilizing Neutralized Bi-Directional Technique Supporting Dual-Polarized MIMO for 5G NR Open
This article presents a low-cost and area-efficient 28-GHz CMOS phased-array beamformer chip for 5G millimeter-wave dual-polarized multiple-in-multiple-out (MIMO) (DP-MIMO) systems. A neutralized bi-directional technique is introduced in t…
View article: A 39-GHz 64-Element Phased-Array Transceiver With Built-In Phase and Amplitude Calibrations for Large-Array 5G NR in 65-nm CMOS
A 39-GHz 64-Element Phased-Array Transceiver With Built-In Phase and Amplitude Calibrations for Large-Array 5G NR in 65-nm CMOS Open
This article presents the first 39-GHz phased-array transceiver (TRX) chipset for fifth-generation new radio (5G NR). The proposed transceiver chipset consists of 4 sub-array TRX elements with local-oscillator (LO) phase-shifting architect…
View article: A 50.1-Gb/s 60-GHz CMOS Transceiver for IEEE 802.11ay With Calibration of LO Feedthrough and I/Q Imbalance
A 50.1-Gb/s 60-GHz CMOS Transceiver for IEEE 802.11ay With Calibration of LO Feedthrough and I/Q Imbalance Open
This paper presents a 60-GHz CMOS transceiver targeting the IEEE 802.11ay standard. A calibration block for local oscillator feedthrough (LOFT) and I/Q imbalance featuring high accuracy and low power consumption is integrated with the tran…
View article: A 0.4-ps-Jitter −52-dBc-Spur Synthesizable Injection-Locked PLL With Self-Clocked Nonoverlap Update and Slope-Balanced Subsampling BBPD
A 0.4-ps-Jitter −52-dBc-Spur Synthesizable Injection-Locked PLL With Self-Clocked Nonoverlap Update and Slope-Balanced Subsampling BBPD Open
In this letter, a fully synthesizable injection-locked phase-locked loop (IL-PLL) is presented. The proposed PLL employed a nonmodified digital standard cell library, and enable fast design migration to other processes. To minimize the ref…
View article: A fully synthesizable injection-locked PLL with feedback current output DAC in 28 nm FDSOI
A fully synthesizable injection-locked PLL with feedback current output DAC in 28 nm FDSOI Open
A feedback current output digital to analog converter (DAC) is proposed to improve the linearity of frequency and reduce the power consumption in this synthesized PLL. All circuit blocks are implemented with standard cells from digital lib…