Bei Yu
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View article: CB-EVO: Contextual Bandit Tuning with Evolutionary Search for Logic Synthesis
CB-EVO: Contextual Bandit Tuning with Evolutionary Search for Logic Synthesis Open
In logic synthesis, pre-optimization involves applying a sequence of transformations, referred to as a synthesis flow, to reduce the complexity of a circuit’s Boolean logic graph, such as the And-Inverter Graph (AIG). The primary challenge…
View article: Stratified GRPO: Handling Structural Heterogeneity in Reinforcement Learning of LLM Search Agents
Stratified GRPO: Handling Structural Heterogeneity in Reinforcement Learning of LLM Search Agents Open
Large language model (LLM) agents increasingly rely on external tools such as search engines to solve complex, multi-step problems, and reinforcement learning (RL) has become a key paradigm for training them. However, the trajectories of s…
View article: MGM-Omni: Scaling Omni LLMs to Personalized Long-Horizon Speech
MGM-Omni: Scaling Omni LLMs to Personalized Long-Horizon Speech Open
We present MGM-Omni, a unified Omni LLM for omni-modal understanding and expressive, long-horizon speech generation. Unlike cascaded pipelines that isolate speech synthesis, MGM-Omni adopts a "brain-mouth" design with a dual-track, token-b…
View article: VisionThink: Smart and Efficient Vision Language Model via Reinforcement Learning
VisionThink: Smart and Efficient Vision Language Model via Reinforcement Learning Open
Recent advancements in vision-language models (VLMs) have improved performance by increasing the number of visual tokens, which are often significantly longer than text tokens. However, we observe that most real-world scenarios do not requ…
View article: Deep-Learning-Based Pre-Layout Parasitic Capacitance Prediction on SRAM Designs
Deep-Learning-Based Pre-Layout Parasitic Capacitance Prediction on SRAM Designs Open
To achieve higher system energy efficiency, SRAM in SoCs is often customized. The parasitic effects cause notable discrepancies between pre-layout and post-layout circuit simulations, leading to difficulty in converging design parameters a…
View article: Rank-DSE: Neural Pareto Comparator of Microarchitecture Design Space Exploration
Rank-DSE: Neural Pareto Comparator of Microarchitecture Design Space Exploration Open
The complexity of microarchitecture design has surged due to the expanding design space and time-intensive verification processes. Existing regression-based machine learning methods struggle with inaccurate estimations because of limited t…
View article: TGDPO: Harnessing Token-Level Reward Guidance for Enhancing Direct Preference Optimization
TGDPO: Harnessing Token-Level Reward Guidance for Enhancing Direct Preference Optimization Open
Recent advancements in reinforcement learning from human feedback have shown that utilizing fine-grained token-level reward models can substantially enhance the performance of Proximal Policy Optimization (PPO) in aligning large language m…
View article: HAPE: Hardware-Aware LLM Pruning For Efficient On-Device Inference Optimization
HAPE: Hardware-Aware LLM Pruning For Efficient On-Device Inference Optimization Open
Over the past few years, large language models (LLMs) have demonstrated remarkable performance and versatility across a variety of complex tasks. However, their deployment has been challenged by their substantial model size and computation…
View article: RTime-QA: A Benchmark for Atomic Temporal Event Understanding in Large Multi-modal Models
RTime-QA: A Benchmark for Atomic Temporal Event Understanding in Large Multi-modal Models Open
Understanding accurate atomic temporal event is essential for video comprehension. However, current video-language benchmarks often fall short to evaluate Large Multi-modal Models' (LMMs) temporal event understanding capabilities, as they …
View article: UniMoCo: Unified Modality Completion for Robust Multi-Modal Embeddings
UniMoCo: Unified Modality Completion for Robust Multi-Modal Embeddings Open
Current research has explored vision-language models for multi-modal embedding tasks, such as information retrieval, visual grounding, and classification. However, real-world scenarios often involve diverse modality combinations between qu…
View article: VisionReasoner: Unified Reasoning-Integrated Visual Perception via Reinforcement Learning
VisionReasoner: Unified Reasoning-Integrated Visual Perception via Reinforcement Learning Open
Large vision-language models exhibit inherent capabilities to handle diverse visual perception tasks. In this paper, we introduce VisionReasoner, a unified framework capable of reasoning and solving multiple visual perception tasks within …
View article: Large Language Models for EDA: Future or Mirage?
Large Language Models for EDA: Future or Mirage? Open
In this article, we explore the burgeoning intersection of large language models (LLMs) and electronic design automation (EDA). We critically assess whether LLMs represent a transformative future for EDA or merely a fleeting mirage. By org…
View article: HDLdebugger: Streamlining HDL debugging with Large Language Models
HDLdebugger: Streamlining HDL debugging with Large Language Models Open
In the domain of chip design, hardware description languages (HDLs) play a pivotal role. However, due to the inherent complexity of HDLs and the scarcity of high-quality debugging resources, HDL bug fixing remains a challenging and time-co…
View article: DiffPattern-Flex: Efficient Layout Pattern Generation via Discrete Diffusion
DiffPattern-Flex: Efficient Layout Pattern Generation via Discrete Diffusion Open
Recent advancements in layout pattern generation have been dominated by deep generative models. However, relying solely on neural networks for legality guarantees raises concerns in many practical applications. In this paper, we present \t…
View article: G-kway: Multilevel GPU-Accelerated k-way Graph Partitioner using Task Graph Parallelism
G-kway: Multilevel GPU-Accelerated k-way Graph Partitioner using Task Graph Parallelism Open
Graph partitioning is important for the design of many CAD algorithms. However, as the graph size continues to grow, graph partitioning becomes increasingly time-consuming. Recent research has introduced parallel graph partitioners using e…
View article: FlexPose: Pose Distribution Adaptation with Limited Guidance
FlexPose: Pose Distribution Adaptation with Limited Guidance Open
Numerous well-annotated human key-point datasets are publicly available to date. However, annotating human poses for newly collected images is still a costly and time-consuming progress. Pose distributions from different datasets share sim…
View article: Bridging Hotspot Detection and Mask Optimization via Domain-Crossing Masked Layout Modeling
Bridging Hotspot Detection and Mask Optimization via Domain-Crossing Masked Layout Modeling Open
With the rapid development of semiconductors, the size of transistors is continuously scaling down. The shrinking circuit size poses great challenges to optical proximity correction (OPC) and hotspot detection (HSD). Recent advancements in…
View article: Ultrasonic Time-of-Flight Diffraction Imaging Enhancement for Pipeline Girth Weld Testing via Time-Domain Sparse Deconvolution and Frequency-Domain Synthetic Aperture Focusing
Ultrasonic Time-of-Flight Diffraction Imaging Enhancement for Pipeline Girth Weld Testing via Time-Domain Sparse Deconvolution and Frequency-Domain Synthetic Aperture Focusing Open
Ultrasonic TOFD imaging, as an important non-destructive testing method, has a wide range of applications in pipeline girth weld inspection and testing. Due to the limited bandwidth of ultrasonic transducers, near-surface defects in the we…
View article: EasyMRC: Efficient Mask Rule Checking via Representative Edge Sampling
EasyMRC: Efficient Mask Rule Checking via Representative Edge Sampling Open
The photolithography process is getting more sophisticated with technology node scaling down and VLSI designs becoming complex. As photomask patterns get finer, mask rule checks (MRCs) are inevitable to avoid discrepancies in the layout an…
View article: GraphCAD: Leveraging Graph Neural Networks for Accuracy Prediction Handling Crosstalk-affected Delays
GraphCAD: Leveraging Graph Neural Networks for Accuracy Prediction Handling Crosstalk-affected Delays Open
View article: HeLO: A <u>He</u> terogeneous <u>L</u> ogic <u>O</u> ptimization Framework by Hierarchical Clustering and Graph Learning
HeLO: A He terogeneous L ogic O ptimization Framework by Hierarchical Clustering and Graph Learning Open
View article: ML-Based Fine-Grained Modeling of DC Current Crowding in Power Delivery TSVs for Face-to-Face 3D ICs
ML-Based Fine-Grained Modeling of DC Current Crowding in Power Delivery TSVs for Face-to-Face 3D ICs Open
View article: Invited: Physical Design for Advanced 3D ICs: Challenges and Solutions
Invited: Physical Design for Advanced 3D ICs: Challenges and Solutions Open
View article: Routing-aware Legal Hybrid Bonding Terminal Assignment for 3D Face-to-Face Stacked ICs
Routing-aware Legal Hybrid Bonding Terminal Assignment for 3D Face-to-Face Stacked ICs Open
Face-to-face (F2F) stacked 3D IC is a promising alternative for scaling beyond Moore’s Law. In F2F 3D ICs, dies are connected through bonding terminals whose positions can significantly impact routing performance. Further, there exists res…
View article: DeepVerifier: Learning to Update Test Sequences for Coverage-Guided Verification
DeepVerifier: Learning to Update Test Sequences for Coverage-Guided Verification Open
Verification is critical in ensuring the reliable operation of modern, complex computing systems. However, as processor designs become increasingly sophisticated, conventional static verification techniques struggle to generate high-qualit…
View article: Architect of the Bits World: Masked Autoregressive Modeling for Circuit Generation Guided by Truth Table
Architect of the Bits World: Masked Autoregressive Modeling for Circuit Generation Guided by Truth Table Open
Logic synthesis, a critical stage in electronic design automation (EDA), optimizes gate-level circuits to minimize power consumption and area occupancy in integrated circuits (ICs). Traditional logic synthesis tools rely on human-designed …
View article: Circuit Representation Learning with Masked Gate Modeling and Verilog-AIG Alignment
Circuit Representation Learning with Masked Gate Modeling and Verilog-AIG Alignment Open
Understanding the structure and function of circuits is crucial for electronic design automation (EDA). Circuits can be formulated as And-Inverter graphs (AIGs), enabling efficient implementation of representation learning through graph ne…
View article: Ultrasonic TOFD Imaging Enhancement Technology for Pipeline Girth Welds Testing via Time Domain Sparse Deconvolution and Frequency Domain Synthetic Aperture Focusing
Ultrasonic TOFD Imaging Enhancement Technology for Pipeline Girth Welds Testing via Time Domain Sparse Deconvolution and Frequency Domain Synthetic Aperture Focusing Open
Ultrasonic TOFD imaging, as an important non-destructive testing method, has a wide range of applications in pipeline girths weld inspection and testing. Due to the limited bandwidth of ultrasonic transducers, near-surface defects in the w…
View article: CMoE: Converting Mixture-of-Experts from Dense to Accelerate LLM Inference
CMoE: Converting Mixture-of-Experts from Dense to Accelerate LLM Inference Open
Scaling large language models (LLMs) improves performance but dramatically increases inference costs. The feed-forward network (FFN), consuming approximately 70\% of inference compute, represents a critical bottleneck, particularly in larg…
View article: TorchResist: Open-Source Differentiable Resist Simulator
TorchResist: Open-Source Differentiable Resist Simulator Open
Recent decades have witnessed remarkable advancements in artificial intelligence (AI), including large language models (LLMs), image and video generative models, and embodied AI systems. These advancements have led to an explosive increase…