Benjamin Carrión Schäfer
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View article: EdgeGuard: Robust and Fault-Aware Design for Resilient Edge Computing AI Accelerators
EdgeGuard: Robust and Fault-Aware Design for Resilient Edge Computing AI Accelerators Open
View article: Improving the Quality of the High-Level Synthesis Estimation Results through Multi-Level Predictive Models
Improving the Quality of the High-Level Synthesis Estimation Results through Multi-Level Predictive Models Open
View article: Efficient and Secure Cloud-based Split Logic Synthesis
Efficient and Secure Cloud-based Split Logic Synthesis Open
View article: HAMMER: Hardware-aware Runtime Program Execution Acceleration through runtime reconfigurable CGRAs
HAMMER: Hardware-aware Runtime Program Execution Acceleration through runtime reconfigurable CGRAs Open
View article: PEPA: Performance Enhancement of Embedded Processors through HW Accelerator Resource Sharing
PEPA: Performance Enhancement of Embedded Processors through HW Accelerator Resource Sharing Open
To improve the performance while reducing the power consumption, embedded processors in Systems-on-Chip (SoC) often now include tightly coupled hardware accelerators that can execute dedicated tasks orders of magnitude more efficiently (fa…
View article: ADVICE: Automatic Design and Optimization of Behavioral Application Specific Processors
ADVICE: Automatic Design and Optimization of Behavioral Application Specific Processors Open
Application Specific Instruction Set Processor (ASIPs) have been proposed in the past to increase the performance while reducing the energy of general-purpose processors. These ASIPs are normally generated at the RT-Level (Verilog or VHDL)…
View article: Building Complete Heterogeneous Systems-on-Chip in C: From Hardware Accelerators to CPUs
Building Complete Heterogeneous Systems-on-Chip in C: From Hardware Accelerators to CPUs Open
High-Level Synthesis (HLS) dramatically accelerates the design and verification of individual components within larger VLSI systems. With most complex Integrated Circuits (ICs) being now heterogeneous Systems-on-Chip (SoCs), HLS has been t…
View article: Functional Obfuscation of Hardware Accelerators through Selective Partial Design Extraction onto an Embedded FPGA
Functional Obfuscation of Hardware Accelerators through Selective Partial Design Extraction onto an Embedded FPGA Open
The protection of Intellectual Property (IP) has emerged as one of the most serious areas of concern in the semiconductor industry. To address this issue, we present a method and architecture to map selective portions of a design, given as…
View article: VHDL vs. SystemC: Design of Highly Parameterizable Artificial Neural Networks
VHDL vs. SystemC: Design of Highly Parameterizable Artificial Neural Networks Open
This paper describes the advantages and disadvantages observed when describing complex parameterizable Artificial Neural Networks (ANNs) at the behavioral level using SystemC and at the Register Transfer Level (RTL) using VHDL. ANNs are co…
View article: Highly parallel scanning tunneling microscope based hydrogen depassivation lithography
Highly parallel scanning tunneling microscope based hydrogen depassivation lithography Open
Hydrogen depassivation lithography (HDL) carried out by a scanning tunneling microscope has sub-nm resolution and the potential to create atomically precise patterns. However, as a serial write tool, it is subject to Tennant’s law which fa…
View article: Implementation of a FPGA-Based Feature Detection and Networking System for Real-time Traffic Monitoring
Implementation of a FPGA-Based Feature Detection and Networking System for Real-time Traffic Monitoring Open
With the growing demand of real-time traffic monitoring nowadays, software-based image processing can hardly meet the real-time data processing requirement due to the serial data processing nature. In this paper, the implementation of a ha…
View article: Recent trends and considerations for high speed data in chips and system interconnects
Recent trends and considerations for high speed data in chips and system interconnects Open
This paper discusses key issues related to the design of large processing volume chip architectures and high speed system interconnects. Design methodologies and techniques are discussed, where recent trends and considerations are highligh…