N. Demaria
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The Impact of Microelectronics on High Energy Physics Innovation: The Role of 65 nm CMOS Technology on New Generation Particle Detectors Open
The High Luminosity Large Hadron Collider (HL-LHC) at CERN will constitute a new frontier for the particle physics after the year 2027. Experiments will undertake a major upgrade in order to stand this challenge: the use of innovative sens…
View article: Characterization of planar and 3D Silicon pixel sensors for the high luminosity phase of the CMS experiment at LHC
Characterization of planar and 3D Silicon pixel sensors for the high luminosity phase of the CMS experiment at LHC Open
The High Luminosity upgrade of the CERN LHC collider (HL-LHC) demands for a new, high-radiation tolerant solid-state pixel sensor capable of surviving fluencies up to a few $10^{16}~ \\rm{n_{eq}/cm^2}$ at $\\sim 3 \\, \\rm{cm} $ from the i…
View article: Test beam characterization of irradiated 3D pixel sensors
Test beam characterization of irradiated 3D pixel sensors Open
Due to the large expected instantaneous luminosity, the future HL-LHC upgrade sets strong requirements on the radiation hardness of the CMS detector Inner Tracker. Sensors based on 3D pixel technology, with its superior radiation tolerance…
View article: RD53A: a large scale prototype for HL-LHC silicon pixel detector phase 2 upgrades
RD53A: a large scale prototype for HL-LHC silicon pixel detector phase 2 upgrades Open
The Phase 2 upgrades of silicon pixel detectors at HL-LHC experiments feature extreme require- ments, such as: 50x50 μm pixels, high rate (3 GHz/cm2), unprecedented radiation levels (1 Grad), high readout speed and serial powering. As a co…
View article: Development of a Large Pixel Chip Demonstrator in RD53 for ATLAS and CMS Upgrades
Development of a Large Pixel Chip Demonstrator in RD53 for ATLAS and CMS Upgrades Open
RD53A is a large scale 65 nm CMOS pixel demonstrator chip that has been developed by the RD53 collaboration for very high rate (3 GHz/cm$^2$) and very high radiation levels (500 Mrad, possibly 1 Grad) for ATLAS and CMS phase 2 upgrades. It…
View article: Results from CHIPIX-FE0, a Small-Scale Prototype of a New Generation Pixel Readout ASIC in 65 nm CMOS for HL-LHC
Results from CHIPIX-FE0, a Small-Scale Prototype of a New Generation Pixel Readout ASIC in 65 nm CMOS for HL-LHC Open
A prototype of a new-generation readout ASIC targeting High-Luminosity (HL) LHC pixel detector upgrades has been designed and fabricated as part of the Italian INFN CHIPIX65 project using a commercial 65 nm CMOS technology. This demonstrat…
MATISSE: a Low Power Front-End Electronics for MAPS Characterization Open
In recent years Monolithic Active Pixel Sensors are becoming increasingly attractive for High Energy Physics experiments. Several R&D activities are ongoing worldwide to improve the performance of conventional monolithic pixels in terms of…
View article: Design of analog front-ends for the RD53 demonstrator chip
Design of analog front-ends for the RD53 demonstrator chip Open
The RD53 collaboration is developing a large scale pixel front-end chip, which will be a tool to\nevaluate the performance of 65 nm CMOS technology in view of its application to the readout\nof the innermost detector layers of ATLAS and CM…
A prototype of pixel readout ASIC in 65 nm CMOS technology for extreme hit rate detectors at HL-LHC Open
This paper describes a readout ASIC prototype designed by the CHIPIX65 project, part of RD53, for a pixel detector at HL-LHC . A 64×64 matrix of $50×50μm^{2}$ pixels is realised. A digital architecture has been developed, with particle eff…
View article: Recent progress of RD53 Collaboration towards next generation Pixel Read-Out Chip for HL-LHC
Recent progress of RD53 Collaboration towards next generation Pixel Read-Out Chip for HL-LHC Open
This paper is a review of recent progress of RD53 Collaboration. Results obtained on the study of the radiation effects on 65 nm CMOS have matured enough to define first strategies to adopt in the design of analog and digital circuits. Cri…
A prototype of a new generation readout ASIC in 65nm CMOS for pixel detectors at HL-LHC Open
The foreseen High-Luminosity upgrade at the CERN Large Hadron Collider (LHC) will constitute a new frontier for particle physics after year 2024, demanding for the installation of new silicon pixel detectors able to withstand unprecedented…
First measurements of a prototype of a new generation pixel readout ASIC in 65 nm CMOS for extreme rate HEP detectors at HL-LHC Open
A first prototype of a readout ASIC in CMOS 65nm for a pixel detector at High Luminosity LHC is described. The pixel cell area is 50x50 um2 and the matrix consists of 64x64 pixels. The chip was designed to guarantee high efficiency at extr…