Explanipedia

Image Colour Correction of Smartphone-based Imaging Devices for Medical Application: A Literature Review Open

Walter C. Low, Yuan Wen Hau, Chia Yee Ooi · 2025

Smartphone technology has revolutionised the field of digital imaging, especially in healthcare and medical applications. Smartphones equipped with built-in high-resolution imaging capabilities, smartphone-based imaging devices have become…

A Word Selection Algorithm for Reliable Enhanced Latency-Based DRAM Physical Unclonable Function Open

Yuin Yee Chew, Wei Liang Lim, Jun Liang Tan, Chia Yee Ooi · 2025

In-Depth Review and Comparative Analysis of DRAM-Based PUFs Open

Yuin Yee Chew, Wei Hong Lim, Jin Tan, Chia Yee Ooi · 2025

Dynamic Random-Access Memory Physical Unclonable Functions (DRAM PUFs) are gaining interest in hardware security, particularly for resource-constrained IoT devices such as smart sensors in the era of rapid digitalization. Since DRAM is pre…

A Review of Machine Learning and Deep Learning Trends in EEG-Based Epileptic Seizure Prediction Open

Yue Wu, Eileen Lee Ming Su, Mingyu Wu, Chia Yee Ooi, William Holderbaum · 2025

Epileptic seizures impair patients’ health and quality of life, and electroencephalography (EEG)-based prediction enables timely intervention. Early work on epileptic seizure prediction employed linear models, whereas recent studies employ…

THERMAL-AWARE TEST SCHEDULING AND FLOOR PLANNING FOR THREE-DIMENSIONAL STACKED INTEGRATED CIRCUITS Open

G. Patmanathan, Chia Yee Ooi, Nagham Ismail, Siti Rahmah Aid · 2024

Testing three-dimensional stacked integrated circuits (3D-SICs) remains a challenging task due to the complexity of generating an optimized test schedule that minimizes test time. One of the main challenges is accessing upper dies, which i…

THERMAL-AWARE TEST SCHEDULING AND FLOOR PLANNING FOR THREE-DIMENSIONAL STACKED INTEGRATED CIRCUITS Open

G. Patmanathan, Chia Yee Ooi, Nagham Ismail, Siti Rahmah Aid · 2024

Testing three-dimensional stacked integrated circuits (3D-SICs) remains a challenging task due to the complexity of generating an optimized test schedule that minimizes test time. One of the main challenges is accessing upper dies, which i…

Data Remanence Based Approach towards Stable Key Generation from Physically Unclonable Function Response of Embedded SRAMs using Binary Search Open

Pyi Phyo Aung, Nordinah Ismail, Chia Yee Ooi, Koichiro Mashiko, Hau Sim Choo , et al. · 2023

Today’s device authentications in IoT devices use public and private key cryptography. Nevertheless, they are still vulnerable to threats because keys or device IDs digitally stored in IoT devices can be stolen or cloned. In contrast, SRAM…

Improving Hardware Trojan Detection Coverage by Utilizing Features at Different Abstraction Levels Open

Hau Sim Choo, Chia Yee Ooi, Nordinah Ismail, Michiko Inoue, Chee Hoo Kok · 2023

In this paper, we introduced a solution to improve hardware Trojan (HT) detection coverage by analyzing features at different abstraction levels. We demonstrated our solution with a supervised classification of HT branching statement (BS) …

Test Scheduling of SoC by using Dynamic Voltage Frequency Scaling (DVFS) Technique Open

Hasliza Hassan, Chia Yee Ooi, Norlina Paraman, Mohd Fadli Kambas · 2022

High temperature gradients in System on Chip (SoC) lowered the performances, reliability and leakage power. In addition, temperature during testing gain more compared to normal operation. Therefore, the investigation of the impact dynamic …

An FPGA-based network system with service-uninterrupted remote functional update Open

Tze Hon Tan, Chia Yee Ooi, Muhammad Nadzir Marsono · 2021

The recent emergence of 5G network enables mass wireless sensors deployment for internet-of-things (IoT) applications. In many cases, IoT sensors in monitoring and data collection applications are required to operate continuously and activ…

Carbon Nanotube Field Effect Transistor (CNTFET) and Resistive Random Access Memory (RRAM) Based Ternary Combinational Logic Circuits Open

Furqan Zahoor, Fawnizu Azmadi Hussin, Farooq A. Khanday, Mohamad Radzi Ahmad, Illani Mohd Nawi , et al. · 2021

The capability of multiple valued logic (MVL) circuits to achieve higher storage density when compared to that of existing binary circuits is highly impressive. Recently, MVL circuits have attracted significant attention for the design of …

Organizing Committee Open

Fawnizu Azmadi Hussin, Michiko Inoue, Chia Yee Ooi, Erik Larsson, Norlina Paraman , et al. · 2020

Program Committee Open

Abu Khari, A. Ain, Alex Orailoğlu, Ankush Srivastava, Baolei Mao , et al. · 2020

Accelerating Extreme Learning Machine on FPGA by Hardware Implementation of Given Rotation-QRD Open

Chong Yeam Tan, Nordinah Ismail, Chia Yee Ooi, Jin Yong Hon · 2019

Currently, Extreme Learning Machine (ELM) is one of the research trends in the machine learning field due to its remarkable performances in terms of complexity and computational speed. However, the big data era and the limitations of gener…

A Customized Reconfiguration Controller with Remote Direct ICAP Access for Dynamically Reconfigurable Platform Open

Tze Hon Tan, Chia Yee Ooi, Muhammad Nadzir Marsono · 2017

As FPGA dynamic partial reconfiguration getting into mainstream, design of reconfiguration controller becomes an active research. Most of the existing reconfiguration controllers support only the loading of partial bitstream into configura…

A Customized Reconfiguration Controller with Remote Direct ICAP Access for Dynamically Reconfigurable Platform Open

Tze Hon Tan, Chia Yee Ooi, Muhammad Nadzir Marsono · 2017

As FPGA dynamic partial reconﬁguration getting into mainstream, design of reconﬁguration controller becomes an active research. Most of the existing reconﬁguration controllers support only the loading of partial bitstream into conﬁguration…

The Design and Implementation of a Low-Power Gating Scan Element in 32/28 nm CMOS Technology Open

Mahshid Mojtabavi Naeini, Sreedharan Baskara Dass, Chia Yee Ooi · 2017

Excessive power consumption during test application time has severely negative effects on chip reliability since it has an inevitable role in hot spots that appear, degradation of performance, circuit premature destruction, and functional …

A Fast SVM-Based Tongue’s Colour Classification Aided by <i>k</i>-Means Clustering Identifiers and Colour Attributes as Computer-Assisted Tool for Tongue Diagnosis Open

Nur Diyana Kamarudin, Chia Yee Ooi, Tadaaki Kawanabe, Hiroshi Odaguchi, Fuminori Kobayashi · 2017

In tongue diagnosis, colour information of tongue body has kept valuable information regarding the state of disease and its correlation with the internal organs. Qualitatively, practitioners may have difficulty in their judgement due to th…

TEST REGISTER INSERTION AT RTL BASED ON REDUCED BIST Open

Norlina Paraman, Chia Yee Ooi, Ahmad Zuri Sha’ameri, Hideo Fujiwara · 2016

Built-in self-test (BIST) method has high area overhead and long test application time. In this paper, a new BIST method is proposed at register transfer level (RTL) as a design for testability (DFT) method to modify a given RTL circuit to…

A FAST AND EFFECTIVE SEGMENTATION ALGORITHM WITH AUTOMATIC REMOVAL OF INEFFECTIVE FEATURES ON TONGUE IMAGES Open

Nur Diyana Kamarudin, Chia Yee Ooi, Tadaaki Kawanabe, Xiaoyu Mi, Hiroshi Odaguchi , et al. · 2016

In computerized tongue diagnostic system, tongue body color has been one of the essential features that contain rich information for diagnosing disease. However, tongue body color measurement can be influenced by the tongue coating color a…

Quantification of tongue colour using machine learning in Kampo medicine Open

Tadaaki Kawanabe, Nur Diyana Kamarudin, Chia Yee Ooi, Fuminori Kobayashi, Xiaoyu Mi , et al. · 2016

The evaluation of tongue colour has been an important approach to examine human health in Kampo medicine (traditional Japanese medicine) because the change in tongue colour may suggest physical or mental disorders. Several tongue colour qu…

A Novel Scan Architecture for Low Power Scan-Based Testing Open

Mahshid Mojtabavi Naeini, Chia Yee Ooi · 2015

Test power has been turned to a bottleneck for test considerations as the excessive power dissipation has serious negative effects on chip reliability. In scan-based designs, rippling transitions caused by test patterns shifting along the …

Low Latency Network-on-Chip Router Microarchitecture Using Request Masking Technique Open

Alireza Monemi, Chia Yee Ooi, Muhammad Nadzir Marsono · 2015

Network-on-Chip (NoC) is fast emerging as an on-chip communication alternative for many-core System-on-Chips (SoCs). However, designing a high performance low latency NoC with low area overhead has remained a challenge. In this paper, we p…

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