Christopher Casares
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View article: LUT-Based Optimization For ASIC Design Flow
LUT-Based Optimization For ASIC Design Flow Open
In this paper, we develop a new LUT-based optimization flow tailored for the synthesis of ASICs rather than FPGAs. We enhance LUT-mapping to consider the literal/AIG cost of LUT-nodes. We extend traditional Boolean methods to simplify and …
View article: SAT-Sweeping Enhanced for Logic Synthesis
SAT-Sweeping Enhanced for Logic Synthesis Open
SAT-sweeping is a powerful method for simplifying logic networks. It consists of merging gates that are proven equivalent (up to complementation) by running simulation and SAT solving in synergy. SAT-sweeping is used in both verification a…
View article: Scalable Boolean Methods in a Modern Synthesis Flow
Scalable Boolean Methods in a Modern Synthesis Flow Open
With the continuous push to improve Quality of Results (QoR) in EDA, Boolean methods in logic synthesis have been recently drawing the attention of researchers. Boolean methods achieve better QoR than algebraic methods but require higher c…