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View article: CSTIC 2023 Cover Page
CSTIC 2023 Cover Page Open
View article: IEEE ELECTRON DEVICES SOCIETY
IEEE ELECTRON DEVICES SOCIETY Open
View article: 3d Backside Integration of Finfets: Is There an Impact on Lf Noise?
3d Backside Integration of Finfets: Is There an Impact on Lf Noise? Open
View article: The European Flagship Conferences ESSDERC and ESSCIRC Merge to Become ESSERC [Conference Reports]
The European Flagship Conferences ESSDERC and ESSCIRC Merge to Become ESSERC [Conference Reports] Open
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View article: IEEE ELECTRON DEVICES SOCIETY
IEEE ELECTRON DEVICES SOCIETY Open
View article: IEEE ELECTRON DEVICES SOCIETY
IEEE ELECTRON DEVICES SOCIETY Open
View article: IEEE Electron Devices Society Information
IEEE Electron Devices Society Information Open
View article: IEEE Electron Devices Society Information
IEEE Electron Devices Society Information Open
View article: Guest Editors' Words
Guest Editors' Words Open
Semiconductor technology has known an exponential evolution during last decades, being the key for the further evolution of micro- and nanoelectronics and the commercial breakthrough of state-of-the-art innovative and sometimes disruptive …
View article: Tunnel-FET Evolution and Applications for Analog Circuits
Tunnel-FET Evolution and Applications for Analog Circuits Open
In this work different generations of field effect tunneling transistor (TFET) are evaluated through DC digital and analog figures of merits. For TFET devices the main digital figure of merit is the subthreshold slope (SS), while for analo…
View article: IEEE Electron Devices Society Information
IEEE Electron Devices Society Information Open
View article: IEEE ELECTRON DEVICES SOCIETY
IEEE ELECTRON DEVICES SOCIETY Open
View article: IEEE ELECTRON DEVICES SOCIETY
IEEE ELECTRON DEVICES SOCIETY Open
View article: IEEE ELECTRON DEVICES SOCIETY
IEEE ELECTRON DEVICES SOCIETY Open
View article: IEEE ELECTRON DEVICES SOCIETY
IEEE ELECTRON DEVICES SOCIETY Open
View article: Impact of gate current on the operational transconductance amplifier designed with nanowire TFETs
Impact of gate current on the operational transconductance amplifier designed with nanowire TFETs Open
View article: Low frequency noise performance of horizontal, stacked and vertical silicon nanowire MOSFETs
Low frequency noise performance of horizontal, stacked and vertical silicon nanowire MOSFETs Open
View article: Detailed low frequency noise assessment on GAA NW n-channel FETs
Detailed low frequency noise assessment on GAA NW n-channel FETs Open
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[Front cover] Open
View article: Analytical Model for Threshold Voltage in UTBB SOI MOSFET in Dynamic Threshold Voltage Operation
Analytical Model for Threshold Voltage in UTBB SOI MOSFET in Dynamic Threshold Voltage Operation Open
This paper presents an analytical model to determine the threshold voltage in Ultrathin Body and Buried Oxide Fully Depleted Silicon on Insulator (UTBB FD SOI) MOSFETs operating in dynamic threshold (DT) voltage modes. The analytical model…
View article: Impact of Gate Stack Layer Composition on Dynamic Threshold Voltage and Analog Parameters of Ge pMOSFETs
Impact of Gate Stack Layer Composition on Dynamic Threshold Voltage and Analog Parameters of Ge pMOSFETs Open
One of the main challenging issues for germanium (Ge) devices is the gate stack engineering which determines the interface state density (NIT) and the associated channel/oxide interface quality. This paper shows how this issue can play a r…
View article: Nanowire Tunnel Field Effect Transistors at High Temperature
Nanowire Tunnel Field Effect Transistors at High Temperature Open
The aim of this work is to study how the performance of nanowire tunnel field effect transistors (TFETs) is influenced by temperature variation. First of all, simulated energy band diagrams were presented to justify its fundamental working…
View article: Observation of the Two-Sided Read Window on UTBOX SOI 1T-DRAM: Measurement Setup, Numerical and Empirical Results
Observation of the Two-Sided Read Window on UTBOX SOI 1T-DRAM: Measurement Setup, Numerical and Empirical Results Open
This paper presents the concept and implementation of a complete 1T-DRAM memory characterization setup and analyzes the read windows of decananometer UTBOX SOI 1T-DRAM memory devices focusing on the mechanisms involved as a function of the…
View article: On the Variability of the Low-Frequency Noise in UTBOX SOI nMOS-FETs
On the Variability of the Low-Frequency Noise in UTBOX SOI nMOS-FETs Open
The variability of the low-frequency (LF) noise in n-channel MOSFETs fabricated on an Ultra-Thin Buried Oxide (UTBOX) Silicon-on-Insulator (SOI) substrate has been studied and compared with the variability in the threshold voltage and low-…
View article: SOI n- and pMuGFET devices with different TiN metal gate thickness and crystallographic orientation of the sidewalls
SOI n- and pMuGFET devices with different TiN metal gate thickness and crystallographic orientation of the sidewalls Open
This work presents an analysis of SOI p- and nMuGFET devices with different TiN metal gate electrode thickness for rotated and standard structures.Thinner TiN metal gate allows achieving a higher intrinsic voltage gain in spite of the redu…
View article: Analog Performance of SOI nMuGFETs with Different TiN Gate Electrode Thickness and High-k Dielectrics
Analog Performance of SOI nMuGFETs with Different TiN Gate Electrode Thickness and High-k Dielectrics Open
This work presents an analysis of the analog performance of SOI MuGFET devices and the impact of different TiN metal gate electrode thickness.Thinner TiN metal gate allows achieving large gain and this effect can be attributed to the incre…
View article: Impact of Selective Epitaxial Growth and Uniaxial/Biaxial Strain on DIBL Effect Using Triple Gate FinFETs
Impact of Selective Epitaxial Growth and Uniaxial/Biaxial Strain on DIBL Effect Using Triple Gate FinFETs Open
The influence of Selective Epitaxial Growth (SEG) and the Uniaxial and Biaxial Strain are studied in triple gate FinFETs, analyzing the Drain Induced Barrier Lowering Effect (DIBL). The splits using SEG present better performance for strai…
View article: Investigation of the Gate Length and Drain Bias Dependence of the ZTC Biasing Point Instability of N- and P-Channel PD SOI MOSFETs
Investigation of the Gate Length and Drain Bias Dependence of the ZTC Biasing Point Instability of N- and P-Channel PD SOI MOSFETs Open
This paper presents an analysis of the instability of the Zero Temperature Coefficient (ZTC) as a function of the gate length and drain bias for partially depleted SOI MOSFETs operating at high temperatures (from room temperature up to 573…
View article: Performance of Source Follower Buffers Implemented with Standard and Strained Triple-Gate nFinFETs
Performance of Source Follower Buffers Implemented with Standard and Strained Triple-Gate nFinFETs Open
In this work the application of standard and strained triple-gate FinFETs in unity-gain source-follower configuration is compared. The analysis is performed by evaluating the buffer voltage gain with respect to the fin width and channel le…
View article: Gate Oxide Thickness Influence on the Gate Induced Floating Body Effect in SOI Technology
Gate Oxide Thickness Influence on the Gate Induced Floating Body Effect in SOI Technology Open
In this work, we explore the gate oxide thickness influence on the Gate Induced Floating Body effect (GIFBE). This study was performed through two-dimensional numerical simulations and electrical measurements. The available devices are fro…