Daniel Chaver
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View article: Teaching Experiences using the RVfpga Package
Teaching Experiences using the RVfpga Package Open
The RVfpga course offers a solid introduction to computer architecture using the RISC-V instruction set and FPGA technology. It focuses on providing hands-on experience with real-world RISC-V cores, the VeeR EH1 and the VeeR EL2, developed…
View article: Reuse Detector: Improving the Management of STT-RAM SLLCs
Reuse Detector: Improving the Management of STT-RAM SLLCs Open
Various constraints of Static Random Access Memory (SRAM) are leading to consider new memorytechnologies as candidates for building on-chip shared last-level caches (SLLCs). Spin-TransferTorque RAM (STT-RAM) is currently postulated as the …