D. Gong
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View article: Investigation of optical properties of Ag nanoparticle aggregates for enhanced solar photothermal conversion
Investigation of optical properties of Ag nanoparticle aggregates for enhanced solar photothermal conversion Open
In solar photothermal conversion technology, nanofluids are widely regarded for their high absorptive capacity and enhanced thermal conductivity. However, nanoparticle aggregation during preparation or dispersion significantly impacts the …
View article: Tolerance of Ge-doped multi-mode fibers in total ionizing dose
Tolerance of Ge-doped multi-mode fibers in total ionizing dose Open
Purpose: The fiber optical links in 850 nm band with Ge-doped multi-mode (MM) fibers are well developed for data transmission at 10 Gbps and higher. The applications in nuclear environments require radiation resistance. The characteristics…
View article: Characteristics of Ge-doped Multi-Mode Fibers in Total Ionizing Dose
Characteristics of Ge-doped Multi-Mode Fibers in Total Ionizing Dose Open
Purpose: The fiber optical links in 850 nm band with Ge-doped multi-mode (MM) fibers are well developed for data transmission at 10 Gbps and higher. The applications in nuclear environments require radiation resistance. The characteristics…
View article: The inter-organelle cross-talk finely orchestrated in the amyloidogenic processing of amyloid precursor protein in dendritic arborization neurons of <i>Drosophila</i>
The inter-organelle cross-talk finely orchestrated in the amyloidogenic processing of amyloid precursor protein in dendritic arborization neurons of <i>Drosophila</i> Open
Background: Organelles in neuronal dendrites facilitate local metabolic processes and energy supply, crucial for dendrite development and neurodegenerative diseases. The distinct functions of dendritic organelles have been well studied, ho…
View article: lpGBT: Low-Power Radiation-Hard Multipurpose High-Speed Transceiver ASIC for High-Energy Physics Experiments
lpGBT: Low-Power Radiation-Hard Multipurpose High-Speed Transceiver ASIC for High-Energy Physics Experiments Open
Commissioning of detector systems for the high-luminosity large Hadron collider (HL-LHC) is scheduled to take place between 2026 and 2028 at CERN. Application-specific integrated circuits (ASICs) for those systems have been in intense deve…
View article: The Single Event Error (SEE) test and analysis of the CMS Endcap Timing Layer readout chip
The Single Event Error (SEE) test and analysis of the CMS Endcap Timing Layer readout chip Open
The ETROC2, the first full size and full functionality prototype chip for the CMS Endcap Timing Layer readout, is strategically designed to meet the SEE immunity requirements of detector operation with the low power constraint. The triplic…
View article: The Compensating Common-Gate Frontend Circuit Used as Current Source Receiver
The Compensating Common-Gate Frontend Circuit Used as Current Source Receiver Open
A very low power frontend circuit using the compensating common-gate scheme is described. It combines features of the regular common-gate topology and the trans-impedance amplifier (TIA) schemes allowing designers to achieve low input impe…
View article: The CMOS Pseudo-Thyristor: A Zero-Static Current Circuit for Pixelized Detector Front-End Stage
The CMOS Pseudo-Thyristor: A Zero-Static Current Circuit for Pixelized Detector Front-End Stage Open
These slides present robotics work at Fermilab and how new robotic technologies are introduced at the lab to encourage better reporting practices within the soft robotic community.
View article: Performance of a front-end prototype ASIC for the ATLAS High Granularity timing detector
Performance of a front-end prototype ASIC for the ATLAS High Granularity timing detector Open
This paper presents the design and characterisation of a front-end prototype ASIC for the ATLAS High Granularity Timing Detector, which is planned for the High-Luminosity phase of the LHC. This prototype, called ALTIROC1, consists of a 5 ×…
View article: GBT20, a 20.48 Gbps PAM4 optical transmitter module for particle physics experiments
GBT20, a 20.48 Gbps PAM4 optical transmitter module for particle physics experiments Open
We present a pluggable radiation-tolerant 4-level Pulse-Amplitude-Modulation (PAM4) optical transmitter module called GBT20 (Giga-Bit Transmitter at 20 Gbps) for particle-physics experiments. GBT20 has an OSFP or firefly connector to input…
View article: An FPGA-based readout chip emulator for the CMS ETL detector upgrade
An FPGA-based readout chip emulator for the CMS ETL detector upgrade Open
We present an FPGA-based readout chip emulator board for the CMS Endcap Timing Layer (ETL) detector upgrade. The emulator board uses an Intel Cyclone 10 GX FPGA to emulate the digital functions of four Endcap Layer Readout Chips (ETROCs). …
View article: TDC with uncontrolled delay lines: calibration approaches and precision improvement methods
TDC with uncontrolled delay lines: calibration approaches and precision improvement methods Open
The time-to-digital-converter (TDC) using uncontrolled delay lines has a simple structure and finer measurement precision since the delay cells are pure digital gates that operate at maximum speed. For every incoming hit, two “snapshots” o…
View article: QTIA, a 2.5 or 10 Gbps 4-channel array optical receiver ASIC in a 65 nm CMOS technology
QTIA, a 2.5 or 10 Gbps 4-channel array optical receiver ASIC in a 65 nm CMOS technology Open
The Quad transimpedance and limiting amplifier (QTIA) is a 4-channel array optical receiver ASIC, developed using a 65 nm CMOS process. It is configurable between the bit rate of 2.56 Gbps and 10 Gbps per channel. QTIA offers careful match…
View article: A prototype optical link board with redundancy design for the ATLAS\n liquid argon calorimeter Phase-2 upgrade
A prototype optical link board with redundancy design for the ATLAS\n liquid argon calorimeter Phase-2 upgrade Open
A prototype optical-link board has been developed for the ATLAS Liquid Argon\nCalorimeter Phase-2 upgrade. The board consists of 24 lpGBT chips and 8 VTRx+\nmodules and demonstrates the full optical link design of the future front-end\nboa…
View article: A 20 Gbps PAM4 data transmitter ASIC for particle physics experiments
A 20 Gbps PAM4 data transmitter ASIC for particle physics experiments Open
We present the design and test results of a novel data transmitter ASIC operating up to 20.48 Gbps with 4-level Pulse-Amplitude-Modulation (PAM4) for particle physics experiments. This ASIC, named GBS20, is fabricated in a 65 nm CMOS techn…
View article: A radiation tolerant clock generator for the CMS endcap timing layer readout chip
A radiation tolerant clock generator for the CMS endcap timing layer readout chip Open
We present the test results of a low jitter Phase Locked Loop (PLL) prototype chip for the CMS Endcap Timing Layer readout chip (ETROC). This chip is based on the improved version of a clock synthesis circuit named ljCDR from the Low Power…
View article: arXiv : A radiation tolerant clock generator for the CMS Endcap Timing Layer readout chip
arXiv : A radiation tolerant clock generator for the CMS Endcap Timing Layer readout chip Open
We present the test results of a low jitter Phase Locked Loop (PLL) prototype chip for the CMS Endcap Timing Layer readout chip (ETROC). This chip is based on the improved version of a clock synthesis circuit named ljCDR from the Low-Power…
View article: arXiv : QTIA, a 2.5 or 10 Gbps 4-Channel Array Optical Receiver ASIC in a 65 nm CMOS Technology
arXiv : QTIA, a 2.5 or 10 Gbps 4-Channel Array Optical Receiver ASIC in a 65 nm CMOS Technology Open
The Quad transimpedance and limiting amplifier (QTIA) is a 4-channel array optical receiver ASIC, developed using a 65 nm CMOS process. It is configurable between the bit rate of 2.56 Gbps and 10 Gbps per channel. QTIA offers careful match…
View article: Characterization and quality control test of a gigabit cable receiver ASIC (GBCR2) for the ATLAS Inner Tracker Detector upgrade
Characterization and quality control test of a gigabit cable receiver ASIC (GBCR2) for the ATLAS Inner Tracker Detector upgrade Open
We present the characterization and quality control test of a gigabit cable\nreceiver ASIC prototype, GBCR2, for the ATLAS Inner Tracker pixel detector\nupgrade. GBCR2 equalizes and retimes the uplink electrical signals from RD53B\nthrough…
View article: Quality control tests of the front-end optical link components for the ATLAS Liquid Argon Calorimeter Phase-1 upgrade
Quality control tests of the front-end optical link components for the ATLAS Liquid Argon Calorimeter Phase-1 upgrade Open
We present the procedures and results of the quality control tests for the front-end optical link components in the ATLAS Liquid Argon Calorimeter Phase-1 upgrade. The components include a Vertical-Cavity Surface-Emitting Laser (VCSEL) dri…
View article: A 10-Gb/s Driver/Receiver ASIC and Optical Modules for Particle Physics Experiments
A 10-Gb/s Driver/Receiver ASIC and Optical Modules for Particle Physics Experiments Open
We present the design and test results of a Drivers and Limiting AmplifierS ASIC operating at 10 Gbps (DLAS10) and three Miniature Optical Transmitter/Receiver/Transceiver modules (MTx+, MRx+, and MTRx+) based on DLAS10. DLAS10 can drive t…
View article: The Analog Front-end for the LGAD Based Precision Timing Application in CMS ETL
The Analog Front-end for the LGAD Based Precision Timing Application in CMS ETL Open
The analog front-end for the Low Gain Avalanche Detector (LGAD) based precision timing application in the CMS Endcap Timing Layer (ETL) has been prototyped in a 65 nm CMOS mini-ASIC named ETROC0. Serving as the very first prototype of ETL …
View article: A novel quad-channel 10 Gbps CMOS VCSEL array driver with integrated charge pumps
A novel quad-channel 10 Gbps CMOS VCSEL array driver with integrated charge pumps Open
We present a novel design and the test results of a 4-channel driver for an array of Vertical-Cavity Surface-Emitting Lasers (VCSELs). This ASIC, named cpVLAD and fabricated in a 65 nm CMOS technology, has on-chip charge pumps and is for d…
View article: A 20 Gbps Data Transmitting ASIC with PAM4 for Particle Physics Experiments
A 20 Gbps Data Transmitting ASIC with PAM4 for Particle Physics Experiments Open
We present the design principle and test results of a data transmitting ASIC, GBS20, for particle physics experiments. The goal of GBS20 will be an ASIC that employs two serializers each from the 10.24 Gbps lpGBT SerDes, sharing the PLL al…
View article: A 10 Gbps Driver/Receiver ASIC and Optical Modules for Particle Physics Experiments
A 10 Gbps Driver/Receiver ASIC and Optical Modules for Particle Physics Experiments Open
We present the design and test results of a Drivers and Limiting AmplifierS ASIC operating at 10 Gbps (DLAS10) and three Miniature Optical Transmitter/Receiver/Transceiver modules (MTx+, MRx+, and MTRx+) based on DLAS10. DLAS10 can drive t…
View article: ETROC1 Design Note. Version 1.0
ETROC1 Design Note. Version 1.0 Open
This document provides the relevant information needed during ETROC1 design integration stage, and it is now improved to be used as a guide for testing ETROC1 prototype chips.
View article: 1.28 and 5.12 Gbps multi-channel twinax cable receiver ASICs for the ATLAS Inner Tracker Pixel Detector Upgrade
1.28 and 5.12 Gbps multi-channel twinax cable receiver ASICs for the ATLAS Inner Tracker Pixel Detector Upgrade Open
We present two prototypes of a gigabit transceiver ASIC, GBCR1 and GBCR2, both designed in a 65-nm CMOS technology for the ATLAS Inner Tracker Pixel Detector readout upgrade. The first prototype, GBCR1, has four upstream receiver channels …