Edian B. Annink
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View article: Preventing Soft Errors and Hardware Trojans in RISC-V Cores
Preventing Soft Errors and Hardware Trojans in RISC-V Cores Open
Soft errors in embedded systems' memories like single-event upsets and multiple-bit upsets lead to data and instruction corruption. Therefore, devices deployed in harsh environments, such as space, use fault-tolerant processors or redundan…
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