Édith Beigné
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View article: Keynotes
Keynotes Open
Augmented reality is a set of technologies that will fundamentally change the way we interact with our environment.It represents a merging of the physical and the digital worlds into a rich, context aware and accessible user interface deli…
View article: Three-Dimensional Stacked Neural Network Accelerator Architectures for AR/VR Applications
Three-Dimensional Stacked Neural Network Accelerator Architectures for AR/VR Applications Open
Three-dimensional integration offers architectural and performance benefits for scaling augmented/virtual reality (AR/VR) models on highly resource-constrained edge devices. Two-dimensional off-chip memory interfaces are too prohibitively …
View article: Session 1 Overview Plenary Session – Invited Papers
Session 1 Overview Plenary Session – Invited Papers Open
Program Chair, Edith Beigne
View article: SamurAI: A 1.7MOPS-36GOPS Adaptive Versatile IoT Node with 15,000× Peak-to-Idle Power Reduction, 207ns Wake-Up Time and 1.3TOPS/W ML Efficiency
SamurAI: A 1.7MOPS-36GOPS Adaptive Versatile IoT Node with 15,000× Peak-to-Idle Power Reduction, 207ns Wake-Up Time and 1.3TOPS/W ML Efficiency Open
International audience
View article: Memory Sizing of a Scalable SRAM In-Memory Computing Tile Based Architecture
Memory Sizing of a Scalable SRAM In-Memory Computing Tile Based Architecture Open
Modern computing applications require more and more data to be processed. Unfortunately, the trend in memory technologies does not scale as fast as the computing performances, leading to the so called memory wall. New architectures are cur…
View article: A 50.5 ns Wake-Up-Latency 11.2 pJ/Inst Asynchronous Wake-Up Controller in FDSOI 28 nm
A 50.5 ns Wake-Up-Latency 11.2 pJ/Inst Asynchronous Wake-Up Controller in FDSOI 28 nm Open
Due to low activity in Internet of Things (IoT) applications, systems tend to leverage low power modes in order to reduce their power consumption. Normally-off computing thus arose, consisting in having turned off most part of a system’s p…
View article: Resistive RAM Endurance: Array-Level Characterization and Correction Techniques Targeting Deep Learning Applications
Resistive RAM Endurance: Array-Level Characterization and Correction Techniques Targeting Deep Learning Applications Open
Limited endurance of resistive RAM (RRAM) is a major challenge for future computing systems. Using thorough endurance tests that incorporate fine-grained read operations at the array level, we quantify for the first time temporary write fa…
View article: ISSCC 2019 Session 14 Overview: Machine Learning and Digital LDO Circuits
ISSCC 2019 Session 14 Overview: Machine Learning and Digital LDO Circuits Open
In this session, seven papers highlight developments in machine learning and digital low-dropout (LDO) linear regulators.The papers demonstrate a hybrid digital and mixed-signal computing platform for swarm robotics, bi-directional memory …
View article: ISSCC 2019 Session 25 Overview: Circuits Enabling Security
ISSCC 2019 Session 25 Overview: Circuits Enabling Security Open
This session focuses on two important aspects of securing hardware systems: 1) authentication, and 2) attack resistance.The first two papers offer new approaches to physically unclonable functions (PUFs), which provide unique keys for secu…
View article: ISSCC 2019 Session 19 Overview: Adaptive Digital and Clocking Techniques
ISSCC 2019 Session 19 Overview: Adaptive Digital and Clocking Techniques Open
This session focuses on circuits that adapt to PVT, workload, and precision requirements, including novel techniques in clocking and digital regulators.The presented adaptive digital and clocking circuits demonstrate minimum energy/power-p…
View article: EE2: How to Save Lives with Circuits
EE2: How to Save Lives with Circuits Open
From healthcare products for an aging population to reliable communications for first responders, circuits are at the heart of products that address pervasive challenges in our world.Circuit innovation can make our lives better, but to tru…
View article: 14.3 A 43pJ/Cycle Non-Volatile Microcontroller with 4.7μs Shutdown/Wake-up Integrating 2.3-bit/Cell Resistive RAM and Resilience Techniques
14.3 A 43pJ/Cycle Non-Volatile Microcontroller with 4.7μs Shutdown/Wake-up Integrating 2.3-bit/Cell Resistive RAM and Resilience Techniques Open
Non-volatility is emerging as an essential on-chip memory characteristic across a wide range of application domains, from edge nodes for the Internet of Things (IoT) to large computing clusters. On-chip non-volatile memory (NVM) is critica…
View article: Energy-Efficient 4T-based SRAM Bitcell for Ultra-Low-Voltage Operations in 28nm 3D CoolCubeTM Technology
Energy-Efficient 4T-based SRAM Bitcell for Ultra-Low-Voltage Operations in 28nm 3D CoolCubeTM Technology Open
This paper presents a 4T-based SRAM bitcell optimized both for write and read operations at ultra-low voltage (ULV). The proposed bitcell is designed to respond to the requirements of energy constrained systems, as in the case of most of t…
View article: A 2.5μW 0.0067mm<sup>2</sup> automatic back-biasing compensation unit achieving 50% leakage reduction in FDSOI 28nm over 0.35-to-1V V<inf>DD</inf> range
A 2.5μW 0.0067mm<sup>2</sup> automatic back-biasing compensation unit achieving 50% leakage reduction in FDSOI 28nm over 0.35-to-1V VDD range Open
International audience
View article: Energy-Efficient Near-Threshold Parallel Computing: The PULPv2 Cluster
Energy-Efficient Near-Threshold Parallel Computing: The PULPv2 Cluster Open
This article presents an ultra-low-power parallel computing platform and its system-on-chip (SoC) embodiment, targeting a wide range of emerging near-sensor processing tasks for Internet of Things (IoT) applications. The proposed SoC achie…
View article: AES Datapath Optimization Strategies for Low-Power Low-Energy Multisecurity-Level Internet-of-Things Applications
AES Datapath Optimization Strategies for Low-Power Low-Energy Multisecurity-Level Internet-of-Things Applications Open
International audience
View article: In-situ Fmax/Vmin tracking for energy efficiency and reliability optimization
In-situ Fmax/Vmin tracking for energy efficiency and reliability optimization Open
Achieving the lowest possible operating voltage is needed to minimize the power consumption of a circuit but also to increase its reliability w.r.t hardware errors. An in-situ technique to estimate and reduce the design margins of a circui…
View article: Ultra Low Energy FDSOI Asynchronous Reconfiguration Network for Adaptive Circuits
Ultra Low Energy FDSOI Asynchronous Reconfiguration Network for Adaptive Circuits Open
This paper introduces a plug-and-play on-chip asynchronous communication network aimed at the dynamic reconfiguration of a low-power adaptive circuit such as an internet of things (IoT) system. By using a separate communication network, we…
View article: High-Density 4T SRAM Bitcell in 14-nm 3-D CoolCube Technology Exploiting Assist Techniques
High-Density 4T SRAM Bitcell in 14-nm 3-D CoolCube Technology Exploiting Assist Techniques Open
In this paper, we present a high-density four-transistor (4T) static random access memory (SRAM) bitcell design for 3-D CoolCube technology platform based on 14-nm fully depleted-silicon on insulator MOS transistors to show the compatibili…
View article: Towards on-line estimation of BTI/HCI-induced frequency degradation
Towards on-line estimation of BTI/HCI-induced frequency degradation Open
International audience
View article: A methodology for the design of dynamic accuracy operators by runtime back bias
A methodology for the design of dynamic accuracy operators by runtime back bias Open
Mobile and IoT applications must balance increasing processing demands with limited power and cost budgets. Approximate computing achieves this goal leveraging the error tolerance features common in many emerging applications to reduce pow…
View article: 193 MOPS/mW @ 162 MOPS, 0.32V to 1.15V voltage range multi-core accelerator for energy efficient parallel and sequential digital processing
193 MOPS/mW @ 162 MOPS, 0.32V to 1.15V voltage range multi-core accelerator for energy efficient parallel and sequential digital processing Open
Low power (mW) and high performance (GOPS) are strong requirements for compute-intensive signal processing in E-health, Internet-of-Things, and wearable applications. This work presents a building block for programmable Ultra-Low Power acc…