Fabien Chaix
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View article: Towards An Approach to Identify Divergences in Hardware Designs for HPC Workloads
Towards An Approach to Identify Divergences in Hardware Designs for HPC Workloads Open
Developing efficient hardware accelerators for mathematical kernels used in scientific applications and machine learning has traditionally been a labor-intensive task. These accelerators typically require low-level programming in Verilog o…
View article: The ExaNeSt Prototype: Evaluation of Efficient HPC Communication Hardware in an ARM-based Multi-FPGA Rack
The ExaNeSt Prototype: Evaluation of Efficient HPC Communication Hardware in an ARM-based Multi-FPGA Rack Open
We present and evaluate the ExaNeSt prototype, which compactly packages 128 Xilinx ZU9EG MPSoCs, two TBytes of DRAM, and eight TBytes of SSD into a liquid-cooled rack, using a custom interconnection hardware based on 10 GB/s links. We deve…
View article: The ExaNeSt Prototype: Evaluation of Efficient HPC Communication Hardware in an ARM-based Multi-FPGA Rack
The ExaNeSt Prototype: Evaluation of Efficient HPC Communication Hardware in an ARM-based Multi-FPGA Rack Open
We present and evaluate the ExaNeSt Prototype, a liquid-cooled rack prototype consisting of 256 Xilinx ZU9EG MPSoCs, 4 TBytes of DRAM, 16 TBytes of SSD, and configurable interconnection 10-Gbps hardware. We developed this testbed in 2016-2…
View article: Optimized Page Fault Handling During RDMA
Optimized Page Fault Handling During RDMA Open
Remote Direct Memory Access (RDMA) is widely used in High-Performance Computing (HPC) while making inroads in datacenters and accelerators. State-of-the-art RDMA engines typically do not endure page faults, therefore users are forced to pi…
View article: Towards resilient EU HPC systems: A blueprint
Towards resilient EU HPC systems: A blueprint Open
This document aims to spearhead a Europe-wide discussion on HPC system resilience and to help the European HPC community define best practices for resilience. We analyse a wide range of state-of-the-art resilience mechanisms and recommend …
View article: Low latency network and distributed storage for next generation HPC systems: the ExaNeSt project
Low latency network and distributed storage for next generation HPC systems: the ExaNeSt project Open
With processor architecture evolution, the HPC market has undergone a paradigm shift. The adoption of low-cost, Linux-based clusters extended the reach of HPC from its roots in modelling and simulation of complex physical systems to a broa…
View article: The ExaNeSt Project: Interconnects, Storage, and Packaging for Exascale Systems
The ExaNeSt Project: Interconnects, Storage, and Packaging for Exascale Systems Open
ExaNest is one of three European projects that support a ground-breaking computing architecture for exascale-class systems built upon power-efficient 64-bit ARM processors. This group of projects share an “everything-close” and “share-anyt…
View article: Optical network technologies for HPC: computer-architects point of view
Optical network technologies for HPC: computer-architects point of view Open
Optical network technologies, such as circuit switching, wavelength division multiplex and silicon photonics, have been considered for high-performance computing (HPC) systems to achieve low communication latency, high link bandwidth and l…