Geert Hellings
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View article: SOT-MRAM Bitcell Scaling With BEOL Read Selectors: A DTCO Study
SOT-MRAM Bitcell Scaling With BEOL Read Selectors: A DTCO Study Open
This work explores the cross-node scaling potential of SOT-MRAM for last-level caches (LLCs) under heterogeneous system scaling paradigm. We perform extensive Design-Technology Co-Optimization (DTCO) exercises to evaluate the bitcell footp…
View article: Exploring GAA-Nanosheet, Forksheet and GAA–Forksheet Architectures: A TCAD-DTCO Study at 90 nm and 120-nm Cell Height
Exploring GAA-Nanosheet, Forksheet and GAA–Forksheet Architectures: A TCAD-DTCO Study at 90 nm and 120-nm Cell Height Open
This study presents a Technology Computer Aided Design (TCAD) and comprehensive Design-Technology Co-Optimization (DTCO) approach to evaluate and enhance power and performance in Gate-All-Around Nanosheet (GAA-Nsh) and Forksheet (Fsh) arch…
View article: Comprehensive DTCO-Driven Power and Performance Optimization in Nanosheet and Forksheet Architectures: Influence of Dielectric Walls, Active Widths, and Power Delivery Methods
Comprehensive DTCO-Driven Power and Performance Optimization in Nanosheet and Forksheet Architectures: Influence of Dielectric Walls, Active Widths, and Power Delivery Methods Open
This study presents a comprehensive Design-Technology Co-Optimization (DTCO) approach to evaluate and enhance power and performance in Gate-All-Around Nanosheet (GAA-Nsh) and Forksheet (Fsh) architectures. The analysis focuses on the impac…
View article: A 1.8-V GPIO With Design-Technology-Reliability Co-Optimization in Sub-3-nm GAA-NS Technology
A 1.8-V GPIO With Design-Technology-Reliability Co-Optimization in Sub-3-nm GAA-NS Technology Open
status: Published
View article: Future Design Direction for SRAM Data Array: Hierarchical Subarray With Active Interconnect
Future Design Direction for SRAM Data Array: Hierarchical Subarray With Active Interconnect Open
status: Published
View article: Physics-Based and Closed-Form Model for Cryo-CMOS Subthreshold Swing
Physics-Based and Closed-Form Model for Cryo-CMOS Subthreshold Swing Open
Cryogenic semiconductor device models are essential in designing control systems for quantum devices and in benchmarking the benefits of cryogenic cooling for high-performance computing. In particular, the saturation of subthreshold swing …
View article: Trapping of Hot Carriers in the Forksheet FET Wall: A TCAD Study
Trapping of Hot Carriers in the Forksheet FET Wall: A TCAD Study Open
sponsorship: The work of M. Vandemaele was supported by the Ph.D. Fellowship of the Research Foundation Flanders (Belgium) under Grant 11A3621N. The review of this letter was arranged by Editor S. Hall. (Corresponding author: M. Vandemaele…
View article: Evaluation of Nanosheet and Forksheet Width Modulation for Digital IC Design in the Sub-3-nm Era
Evaluation of Nanosheet and Forksheet Width Modulation for Digital IC Design in the Sub-3-nm Era Open
In this article, we provide a comprehensive evaluation of width modulation capabilities of both nanosheet (NS) and forksheet (FS) devices, going from device level to a block level implementation. The main innovation introduced by the FS co…
View article: Backside PDN and 2.5D MIMCAP to Double Boost 2D and 3D ICs IR-Drop beyond 2nm Node
Backside PDN and 2.5D MIMCAP to Double Boost 2D and 3D ICs IR-Drop beyond 2nm Node Open
In this paper, backside power delivery network (BS-PDN) and a high density 2.5D Mimcap (Metal-insulator-metal capacitor) are applied to improve dynamic IR-drop of 2D and 3D ICs at a sub-2nm node. An on-chip PDN design and IR drop modelling…
View article: Design and Optimization of SRAM Macro and Logic Using Backside Interconnects at 2nm node
Design and Optimization of SRAM Macro and Logic Using Backside Interconnects at 2nm node Open
In this work, we explore the resource of backside (BS) interconnect for signal routing in SRAM macro and logic at 2nm technology node to tackle the technology scaling induced frontside (FS) BEOL routing congestion challenge. High-Aspect ra…
View article: Processing Impact on the Low-Frequency Noise of 1.8V Input-Output Bulk FinFETs
Processing Impact on the Low-Frequency Noise of 1.8V Input-Output Bulk FinFETs Open
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View article: Bi-Modal Variability of nFinFET Characteristics During Hot-Carrier Stress: A Modeling Approach
Bi-Modal Variability of nFinFET Characteristics During Hot-Carrier Stress: A Modeling Approach Open
sponsorship: This work was supported in part by the European Union's Horizon 2020 Research and Innovation Programme through the Marie Sklodowska-Curie Grant 794950 and in part by the Austrian Science Fund (FWF) under Grant P31204-N30. (Eur…
View article: Stochastic Modeling of the Impact of Random Dopants on Hot-Carrier Degradation in n-FinFETs
Stochastic Modeling of the Impact of Random Dopants on Hot-Carrier Degradation in n-FinFETs Open
sponsorship: This work was supported in part by the European Union's Horizon 2020 Research and Innovation Programme through the Marie Sklodowska-Curie under Grant 794950 and in part by the Austrian Science Fund (FWF) under Grant P31204-N30…
View article: ESD study on a-IGZO TFT device architectures
ESD study on a-IGZO TFT device architectures Open
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View article: Анализ особенностей деградации, вызываемой горячими носителями, в транзисторах с каналом в форме плавника
Анализ особенностей деградации, вызываемой горячими носителями, в транзисторах с каналом в форме плавника Open
For the first time, hot-carrier degradation (HCD) is simulated in non-planar field-effect transistors with a fin-shaped channel (FinFETs). For this purpose, a physical model considering single-carrier and multiple-carrier silicon–hydrogen …
View article: ESD protection design in a-IGZO TFT technologies
ESD protection design in a-IGZO TFT technologies Open
<p>Thin Film Transistor (TFT) with amorphous Indium-Gallium-Zinc-Oxide (a-IGZO) as channel material are characterized with TLP and HBM testing. The low mobility of the a-IGZO channel results in an ESD robustness of only 0.3 mA/um. Th…