Gordon W. Roberts
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View article: Design for Slew-Rate in Multi-Stage CMOS OTAs
Design for Slew-Rate in Multi-Stage CMOS OTAs Open
View article: Design for Slew-Rate in Multi-Stage CMOS OTAs
Design for Slew-Rate in Multi-Stage CMOS OTAs Open
View article: Applying Nyquist’s Stability Analysis to Bode Plots With Wrapped Phase Behavior
Applying Nyquist’s Stability Analysis to Bode Plots With Wrapped Phase Behavior Open
This paper describes the stability conditions of Nyquist in terms of the data related to a Bode plot of the loop transmission function Aβ(jω). Specifically, it will be shown that the number of encirclements of Aβ(jω) around the critical po…
View article: Scalable Multi-Stage CMOS OTAs With a Wide C<sub>L</sub>-Drivability Range Using Low-Frequency Zeros
Scalable Multi-Stage CMOS OTAs With a Wide C<sub>L</sub>-Drivability Range Using Low-Frequency Zeros Open
This work introduces a multi-stage CMOS OTA design technique that allows cascading identical gain stages (for arbitrarily scalable high DC gain) while driving an ultra-wide range of capacitive loads ( ). At the heart of the proposed desig…
View article: Identifying A(s) and β(s) in Single-Loop Feedback Circuits Using the Intermediate Transfer Function Approach
Identifying A(s) and β(s) in Single-Loop Feedback Circuits Using the Intermediate Transfer Function Approach Open
It is common practice to model the input–output behavior of a single-loop feedback circuit using the two parameters, A and β. Such an approach was first proposed by Black to explain the advantages and disadvantages of negative feedback. Ex…
View article: Generalized Relationship Between Frequency Response and Settling Time of CMOS OTAs: Toward Many-Stage Design
Generalized Relationship Between Frequency Response and Settling Time of CMOS OTAs: Toward Many-Stage Design Open
The presence of Pole-Zero (P-Z) pairs in the open-loop frequency response of CMOS OTAs has always been considered detrimental to the closed-loop operation of OTAs. In this work, a new proposed theory is presented showing how to reduce the …
View article: A 36 MW, 13 B, 2.1 MS/S MULTI-BIT DS ADC IN 0.18 M DIGITAL CMOS PROCESS USING AN EFFICIENT TOP-DOWN DESIGN METHODOLOGY
A 36 MW, 13 B, 2.1 MS/S MULTI-BIT DS ADC IN 0.18 M DIGITAL CMOS PROCESS USING AN EFFICIENT TOP-DOWN DESIGN METHODOLOGY Open
A systematic method to design a switched-capacitor (SC) multi-bit DS ADC integrated circuit is presented. The modulator consists of a fourth-order, multi-stage (2-1-1) architecture, with a 3-bit fash ADC in the last stage only. The modulat…
View article: TIME-INTERLEAVED MIXED-SIGNAL TEST CORE DIGITIZERS
TIME-INTERLEAVED MIXED-SIGNAL TEST CORE DIGITIZERS Open
System-on-Chip (SoC) is one of the main driving forces that have been re-shaping the consumer electronics industry. The SoC alternative to conventional systems design is growing in popularity as the device packing densi escalates due to th…
View article: A 19 MW, 12.5 B, 2.1 MS/S SINGLE-BIT DS ADC IN 0.18 MM DIGITAL CMOS PROCESS
A 19 MW, 12.5 B, 2.1 MS/S SINGLE-BIT DS ADC IN 0.18 MM DIGITAL CMOS PROCESS Open
The increasingly stringent requirements of today’s communication systems and portable devices are imposing two challenges on the design of high-resolution, high-speed ADCs and delta-sigma modulators (DSMs) in particular. The first is the e…
View article: Optimized Periodic ΣΔ Bitstreams for DC Signal Generation Used in Dynamic Calibration Applications
Optimized Periodic ΣΔ Bitstreams for DC Signal Generation Used in Dynamic Calibration Applications Open
Settling time is an important performance metric in digital-to-analog converters (DACs) that are used for dynamic calibration applications. To obtain an area efficient DAC design, periodic sequences are generated from sigma-delta modulator…
View article: A Jitter Injection Signal Generation and Extraction System for Embedded Test of High-Speed Data I/O
A Jitter Injection Signal Generation and Extraction System for Embedded Test of High-Speed Data I/O Open
An instrument for on-chip measurement of transceiver transmission capability is described that is fully realizable in CMOS technology and embeddable within an SoC. The instrument can be used to inject and extract the timing and voltage inf…
View article: Guest Editors' Introduction: Speeding Up Analog Integration and Test for Mixed-Signal SoCs
Guest Editors' Introduction: Speeding Up Analog Integration and Test for Mixed-Signal SoCs Open
The seven articles in this special section initiatives to standardize methods, measurements, and tools that support mixed-signal design. The papers are organized along the lines of the overall design-to-test flow, covering verification, se…