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View article: EDHPC 2023 Cover Page
EDHPC 2023 Cover Page Open
This tutorial explores developing a Deep Neural Network (DNN) algorithm leveraging FPGAs for space applications.It covers the deployment of DNN on FPGA platforms to accelerate tasks such as image analysis, object recognition, and data proc…
View article: DVINO: A RISC-V Vector Processor Implemented in 65nm Technology
DVINO: A RISC-V Vector Processor Implemented in 65nm Technology Open
This paper describes the design, verification, implementation and fabrication of the Drac Vector IN-Order (DVINO) processor, a RISC-V vector processor capable of booting Linux jointly developed by BSC, CIC-IPN, IMB-CNM (CSIC), and UPC. The…
View article: End-to-End QoS for the Open Source Safety-Relevant RISC-V SELENE Platform
End-to-End QoS for the Open Source Safety-Relevant RISC-V SELENE Platform Open
This paper presents the end-to-end QoS approach to provide performance guarantees followed in the SELENE platform, a high-performance RISC-V based heterogeneous SoC for safety-related real-time systems. Our QoS approach includes smart inte…
View article: SafeSoftDR: A Library to Enable Software-based Diverse Redundancy for Safety-Critical Tasks
SafeSoftDR: A Library to Enable Software-based Diverse Redundancy for Safety-Critical Tasks Open
Applications with safety requirements have become ubiquitous nowadays and can be found in edge devices of all kinds. However, microcontrollers in those devices, despite offering moderate performance by implementing multicores and cache hie…
View article: SafeX: Open Source Hardware and Software Components for Safety-Critical Systems
SafeX: Open Source Hardware and Software Components for Safety-Critical Systems Open
RISC-V Instruction Set Architecture (ISA) emerges as an opportunity to develop open source hardware without being subject to expensive licenses or export restrictions. A plethora of initiatives are nowadays developing systems-on-chip (SoCs…
View article: Unboxing the Sand: on Deploying Safety Measures in the Programmable Logic of COTS MPSoCs
Unboxing the Sand: on Deploying Safety Measures in the Programmable Logic of COTS MPSoCs Open
View article: De-RISC: A Complete RISC-V Based Space-Grade Platform
De-RISC: A Complete RISC-V Based Space-Grade Platform Open
The H2020 EIC-FTI De-RISC project develops a RISC-V space-grade platform to jointly respond to several emerging, as well as longstanding needs in the space domain such as: (1) higher performance than that of monocore and basic multicore sp…
View article: SafeDM: a Hardware Diversity Monitor for Redundant Execution on Non-Lockstepped Cores
SafeDM: a Hardware Diversity Monitor for Redundant Execution on Non-Lockstepped Cores Open
Computing systems in the safety domain, such as those in avionics or space, require specific safety measures related to the criticality of the deployment. A problem these systems face is that of transient failures in hardware. A solution c…
View article: SafeSU-2: a Safe Statistics Unit for Space MPSoCs
SafeSU-2: a Safe Statistics Unit for Space MPSoCs Open
Advanced statistics units (SUs) have been proven effective for the verification, validation and implementation of safety measures as part of safety-related MPSoCs. This is the case, for instance, of the RISC-V MPSoC by CAES Gaisler based o…
View article: SafeDE: A Low-Cost Hardware Solution to Enforce Diverse Redundancy in Multicores
SafeDE: A Low-Cost Hardware Solution to Enforce Diverse Redundancy in Multicores Open
Failure risk must be tiny in high-integrity systems, such as those in cars, satellites and aircraft. Hence, safety measures must be deployed to avoid a single fault leading to a failure. Redundancy has been often used to address this conce…
View article: De-RISC: Dependable Real-time RISC-V Infrastructure for Safety-critical Space and Avionics Computer Systems
De-RISC: Dependable Real-time RISC-V Infrastructure for Safety-critical Space and Avionics Computer Systems Open
The world market for aviation and space computing systems faces a significant shift caused by the loss of momentum of the traditionally used PowerPC and SPARC instruction set architectures in the commercial domain. This means that the spac…
View article: De-RISC: the First RISC-V Space-Grade Platform for Safety-Critical Systems
De-RISC: the First RISC-V Space-Grade Platform for Safety-Critical Systems Open
The increasing needs for performance in the space domain for highly autonomous systems calls for more powerful space MPSoCs and appropriate hypervisors to master them. These platforms must adhere to strict reliability, verifiability and va…
View article: SafeTI: a Hardware Traffic Injector for MPSoC Functional and Timing Validation
SafeTI: a Hardware Traffic Injector for MPSoC Functional and Timing Validation Open
Functional and timing validation of safety-related MPSoCs requires testing specific traffic patterns in the on-chip interconnects. Generally, testing needs to be performed by using software tests whose degree of control on the traffic gene…
View article: SafeDE: a flexible Diversity Enforcement hardware module for light-lockstepping
SafeDE: a flexible Diversity Enforcement hardware module for light-lockstepping Open
Safety-related systems, such as those in automotive, avionics and space, impose the existence of appropriate safety measures to meet the safety requirements of the system. In the case of the highest integrity level functionalities (e.g. AS…
View article: SafeSU: an Extended Statistics Unit for Multicore Timing Interference
SafeSU: an Extended Statistics Unit for Multicore Timing Interference Open
Statistics units (SUs) in MPSoCs are becoming increasingly used for the (1) verification and (2) validation of multicore timing interference, as well as for (3) deploying safety measures in safety-related real-time systems. However, existi…
View article: An Academic RISC-V Silicon Implementation Based on Open-Source Components
An Academic RISC-V Silicon Implementation Based on Open-Source Components Open
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