Ipoom Jeong
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A4: Microarchitecture-Aware LLC Management for Datacenter Servers with Emerging I/O Devices Open
In modern server CPUs, the Last-Level Cache (LLC) serves not only as a victim cache for higher-level private caches but also as a buffer for low-latency DMA transfers between CPU cores and I/O devices through Direct Cache Access (DCA). How…
A Quantitative Analysis and Guidelines of Data Streaming Accelerator in Modern Intel Xeon Scalable Processors Open
As semiconductor power density is no longer constant with the technology process scaling down, we need different solutions if we are to continue scaling application performance. To this end, modern CPUs are integrating capable data acceler…
View article: Demystifying CXL Memory with Genuine CXL-Ready Systems and Devices
Demystifying CXL Memory with Genuine CXL-Ready Systems and Devices Open
This code release includes testings scripts for some figures, our benchmark Memo, and our tuning scheme Caption.
A Quantitative Analysis and Guidelines of Data Streaming Accelerator in Modern Intel Xeon Scalable Processors Open
As semiconductor power density is no longer constant with the technology process scaling down, modern CPUs are integrating capable data accelerators on chip, aiming to improve performance and efficiency for a wide range of applications and…
TEA-RC: Thread Context-Aware Register Cache for GPUs Open
Graphics processing units (GPUs) achieve high throughput by exploiting a high degree of thread-level parallelism (TLP). To support such high TLP, GPUs have a large-sized register file to store the context of all threads, consuming around 2…