Jackson Melchert
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View article: PEak: A Single Source of Truth for Hardware Design and Verification
PEak: A Single Source of Truth for Hardware Design and Verification Open
Domain-specific languages for hardware can significantly enhance designer productivity, but sometimes at the cost of ease of verification. On the other hand, ISA specification languages are too static to be used during early stage design s…
View article: Efficiently Synthesizing Lowest Cost Rewrite Rules for Instruction Selection
Efficiently Synthesizing Lowest Cost Rewrite Rules for Instruction Selection Open
Compiling programs to an instruction set architecture (ISA) requires a set of rewrite rules that map patterns consisting of compiler instructions to patterns consisting of ISA instructions. We synthesize such rules by constructing SMT quer…
View article: PEak: A Single Source of Truth for Hardware Design and Verification
PEak: A Single Source of Truth for Hardware Design and Verification Open
Domain-specific languages for hardware can significantly enhance designer productivity, but sometimes at the cost of ease of verification. On the other hand, ISA specification languages are too static to be used during early stage design s…
View article: Canal: A Flexible Interconnect Generator for Coarse-Grained Reconfigurable Arrays
Canal: A Flexible Interconnect Generator for Coarse-Grained Reconfigurable Arrays Open
The architecture of a coarse-grained reconfigurable array (CGRA) interconnect has a significant effect on not only the flexibility of the resulting accelerator, but also its power, performance, and area. Design decisions that have complex …
View article: Cascade: An Application Pipelining Toolkit for Coarse-Grained Reconfigurable Arrays
Cascade: An Application Pipelining Toolkit for Coarse-Grained Reconfigurable Arrays Open
While coarse-grained reconfigurable arrays (CGRAs) have emerged as promising programmable accelerator architectures, pipelining applications running on CGRAs is required to ensure high maximum clock frequencies. Current CGRA compilers eith…
View article: Automated Design Space Exploration of CGRA Processing Element Architectures using Frequent Subgraph Analysis
Automated Design Space Exploration of CGRA Processing Element Architectures using Frequent Subgraph Analysis Open
The architecture of a coarse-grained reconfigurable array (CGRA) processing element (PE) has a significant effect on the performance and energy efficiency of an application running on the CGRA. This paper presents an automated approach for…
View article: A Comparative Study of Local Net Modeling Using Machine Learning
A Comparative Study of Local Net Modeling Using Machine Learning Open
Local nets are by default ignored during global routing but can contribute to a high percentage (up to 30%) of total number of nets in the design. Prior work proposed simple models for how local nets are routed and showed benefits such as …