Jason H. Anderson
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View article: GRAMM: Fast CGRA Application Mapping Based on A Heuristic for Finding Graph Minors
GRAMM: Fast CGRA Application Mapping Based on A Heuristic for Finding Graph Minors Open
A graph H is a minor of a second graph G if G can be transformed into H by two operations: 1) deleting nodes and/or edges, or 2) contracting edges. Coarse-grained reconfigurable array (CGRA) application mapping is closely related to the gr…
View article: Efficient Memory Arbitration in High-Level Synthesis From Multi-Threaded Code
Efficient Memory Arbitration in High-Level Synthesis From Multi-Threaded Code Open
High-level synthesis (HLS) is an increasingly popular method for generating hardware from a description written in a software language like C/C++. Traditionally, HLS tools have operated on sequential code, however in recent years there has…
View article: Generic Connectivity-Based CGRA Mapping via Integer Linear Programming
Generic Connectivity-Based CGRA Mapping via Integer Linear Programming Open
Coarse-grained reconfigurable architectures (CGRAs) are programmable logic devices with large coarse-grained ALU-like logic blocks, and multi-bit datapath-style routing. CGRAs often have relatively restricted data routing networks, so they…
View article: Dataset for EASY: Efficient Arbiter SYnthesis from Multi-threaded Code
Dataset for EASY: Efficient Arbiter SYnthesis from Multi-threaded Code Open
High-level synthesis (HLS) is an increasingly popular method for generating hardware from a description written in a software language like C/C++. Traditionally, HLS tools have operated on sequential code, however in recent years there has…
View article: Dataset for EASY: Efficient Arbiter SYnthesis from Multi-threaded Code
Dataset for EASY: Efficient Arbiter SYnthesis from Multi-threaded Code Open
High-level synthesis (HLS) is an increasingly popular method for generating hardware from a description written in a software language like C/C++. Traditionally, HLS tools have operated on sequential code, however in recent years there has…
View article: FPGA-based CNN inference accelerator synthesized from multi-threaded C software
FPGA-based CNN inference accelerator synthesized from multi-threaded C software Open
A deep-learning inference accelerator is synthesized from a C-language\nsoftware program parallelized with Pthreads. The software implementation uses\nthe well-known producer/consumer model with parallel threads interconnected by\nFIFO que…