Jawar Singh
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View article: Design and performance assessment of dielectric modulated N <mml:math xmlns:mml="http://www.w3.org/1998/Math/MathML" altimg="si35.svg" display="inline" id="d1e1155"> <mml:msup> <mml:mrow/> <mml:mrow> <mml:mo>+</mml:mo> </mml:mrow> </mml:msup> </mml:math> P <mml:math xmlns:mml="http://www.w3.org/1998/Math/MathML" altimg="si35.svg" display="inline" id="d1e1163"> <mml:msup> <mml:mrow/> <mml:mrow> <mml:mo>+</mml:mo> </mml:mrow> </mml:msup> </mml:math> I N <mml:math xmlns:mml="http://www.w3.org/1998/Math/MathML" altimg="si35.svg" display="inline" id="d1e1171"> <mml:msup> <mml:mrow/> <mml:mrow> <mml:mo>+</mml:mo> </mml:mrow> </mml:msup> </mml:math> P <mml:math xmlns:mml="http://www.w3.org/1998/Math/MathML" altimg="si35.svg" display="inline" id="d1e1180"> <mml:msup> <mml:mrow/> <mml:mrow> <mml:mo>+</mml:mo> </mml:mrow> </mml:msup> </mml:math> feedback FET based biosensor
Design and performance assessment of dielectric modulated N P I N P feedback FET based biosensor Open
View article: Securing IIoT systems against DDoS attacks with adaptive moving target defense strategies
Securing IIoT systems against DDoS attacks with adaptive moving target defense strategies Open
View article: Design and performance analysis of tri-layered strained Si/Si<sub>1–<i>x</i> </sub>Ge<sub> <i>x</i> </sub>/Si heterostructure DG feedback FET
Design and performance analysis of tri-layered strained Si/Si<sub>1–<i>x</i> </sub>Ge<sub> <i>x</i> </sub>/Si heterostructure DG feedback FET Open
This work presents the design and performance analysis of a tri-layered strained Si/Si 1− x Ge x /Si heterostructure double gate feedback field-effect transistor (DG FBFET). The proposed DG FBFET is designed by introducing biaxial strain i…
View article: Design and performance analysis of Si-SiGe heterostructure based double gate feedback FET
Design and performance analysis of Si-SiGe heterostructure based double gate feedback FET Open
The design and performance analysis of a Si-SiGe heterostructure-based double gate feedback field-effect transistor (HDG FBFET) are presented in this paper. The proposed HDG FBFET is capable of providing high on current (3 × 10 −4 A/ μ m) …
View article: Benchmarking of Multi-Bridge-Channel FETs Toward Analog and Mixed-Mode Circuit Applications
Benchmarking of Multi-Bridge-Channel FETs Toward Analog and Mixed-Mode Circuit Applications Open
In this study, for the very first time developing of n- and p-type 3-D single-channel (SC) FinFET and gate-all-around (GAA) Multi-Bridge-Channel FETs (MBCFET) like nanowire FET (NWFET) and nanosheet FET (NSFET) are benchmarked towards devi…
View article: Analog and mixed circuit analysis of nanosheet FET at elevated temperatures
Analog and mixed circuit analysis of nanosheet FET at elevated temperatures Open
In this paper, for the first time, the performance of 3D Nanosheet FETs (NSFETs) is reported in the inversion (INV), accumulation (ACC), and junctionless (JL) modes at elevated temperatures. It is observed that, as the temperature increase…
View article: Exploring the Performance of 3-D Nanosheet FET in Inversion and Junctionless Modes: Device and Circuit-Level Analysis and Comparison
Exploring the Performance of 3-D Nanosheet FET in Inversion and Junctionless Modes: Device and Circuit-Level Analysis and Comparison Open
In this article, the performance of 3-D nanosheet FET (NS-FET) in inversion (INV) and junctionless (JL) modes is demonstrated and compared at both device and circuit levels. In JL mode, the ON current () rises with an increase in temperatu…
View article: Design and analysis of DDoS mitigating network architecture
Design and analysis of DDoS mitigating network architecture Open
View article: In-memory Implementation of On-chip Trainable and Scalable ANN for AI/ML Applications
In-memory Implementation of On-chip Trainable and Scalable ANN for AI/ML Applications Open
Traditional von Neumann architecture based processors become inefficient in terms of energy and throughput as they involve separate processing and memory units, also known as~\textit{memory wall}. The memory wall problem is further exacerb…
View article: Improvement in Retention Time of Capacitorless DRAM with Access Transistor
Improvement in Retention Time of Capacitorless DRAM with Access Transistor Open
In this paper, we propose a Junctionless (JL)/Accumulation Mode (AM) transistor with an access transistor (JL in series with JL/AM transistor) based capacitorless Dynamic Random Access Memory (1TDRAM) cell. The JL transistor overcomes the …
View article: Ultra-Low Energy and High Speed LIF Neuron using Silicon Bipolar Impact\n Ionization MOSFET for Spiking Neural Networks
Ultra-Low Energy and High Speed LIF Neuron using Silicon Bipolar Impact\n Ionization MOSFET for Spiking Neural Networks Open
Silicon bipolar impact ionization MOSFET offers the potential for realization\nof leaky integrated fire (LIF) neuron due to the presence of parasitic BJT in\nthe floating body. In this work, we have proposed an L shaped gate bipolar\nimpac…
View article: Ultra-Low Energy and High Speed LIF Neuron using Silicon Bipolar Impact Ionization MOSFET for Spiking Neural Networks
Ultra-Low Energy and High Speed LIF Neuron using Silicon Bipolar Impact Ionization MOSFET for Spiking Neural Networks Open
Silicon bipolar impact ionization MOSFET offers the potential for realization of leaky integrated fire (LIF) neuron due to the presence of parasitic BJT in the floating body. In this work, we have proposed an L shaped gate bipolar impact i…
View article: Energy and Area Aware Digital Fingerprint Generator Using Intrinsic Randomness
Energy and Area Aware Digital Fingerprint Generator Using Intrinsic Randomness Open
View article: Analog/RF Performance Investigation of Dopingless FET for Ultra-Low Power Applications
Analog/RF Performance Investigation of Dopingless FET for Ultra-Low Power Applications Open
In this paper, we investigated the performance of a dopingless (DL) double gate fieldeffect transistor (DL-DGFET) for ultra-low power (ULP) analog/RF applications. It is observed that the source/drain metal electrode work-function engineer…
View article: Electrostatically Doped Heterojunction TFET with Enhanced Driving\n Capabilities for Low Power Applications
Electrostatically Doped Heterojunction TFET with Enhanced Driving\n Capabilities for Low Power Applications Open
This paper projects the enhanced drive current of a n-type electrostatically\ndoped (ED) tunnel field-effect transistor (ED-TFET) based on heterojunction and\nband-gap engineering via TCAD 2-D device simulations. The homojunction ED-TFET\n…
View article: Electrostatically Doped Heterojunction TFET with Enhanced Driving Capabilities for Low Power Applications
Electrostatically Doped Heterojunction TFET with Enhanced Driving Capabilities for Low Power Applications Open
This paper projects the enhanced drive current of a n-type electrostatically doped (ED) tunnel field-effect transistor (ED-TFET) based on heterojunction and band-gap engineering via TCAD 2-D device simulations. The homojunction ED-TFET dev…
View article: Electrically doped dynamically configurable field‐effect transistor for low‐power and high‐performance applications
Electrically doped dynamically configurable field‐effect transistor for low‐power and high‐performance applications Open
The concept of an electrically doped dynamically configurable field‐effect transistor (FET) is presented, which provides freedom to dynamically switch between a high‐performance MOSFET and a low‐power tunnel FET that can be ideal for compl…
View article: Symmetric bipolar charge‐plasma transistor with extruded base for enhanced performance
Symmetric bipolar charge‐plasma transistor with extruded base for enhanced performance Open
A new structure for a symmetric bipolar charge‐plasma transistor device with an extruded base is proposed. The charge plasma and extruded base concepts are used to increase the current gain and cutoff frequency of the proposed device, resp…
View article: A 0.6 V, low‐power and high‐gain ultra‐wideband low‐noise amplifier with forward‐body‐bias technique for low‐voltage operations
A 0.6 V, low‐power and high‐gain ultra‐wideband low‐noise amplifier with forward‐body‐bias technique for low‐voltage operations Open
A two‐stage common‐source (CS) low‐noise amplifier (LNA) that uses a forward‐body‐bias technique in N‐type metal–oxide semiconductor devices and intended to achieve a high gain and low power consumption is proposed in this study for ultra‐…