Jayesh Gaur
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View article: Constable: Improving Performance and Power Efficiency by Safely Eliminating Load Instruction Execution
Constable: Improving Performance and Power Efficiency by Safely Eliminating Load Instruction Execution Open
Load instructions often limit instruction-level parallelism (ILP) in modern processors due to data and resource dependences they cause. Prior techniques like Load Value Prediction (LVP) and Memory Renaming (MRN) mitigate load data dependen…
View article: Cryptographic Capability Computing
Cryptographic Capability Computing Open
Capability architectures for memory safety have traditionally required expanding pointers and radically changing microarchitectural structures throughout processors, while only providing superficial hardening. We hence propose Cryptographi…
View article: MARS: Memory Aware Reordered Source
MARS: Memory Aware Reordered Source Open
Memory bandwidth is critical in today's high performance computing systems. The bandwidth is particularly paramount for GPU workloads such as 3D Gaming, Imaging and Perceptual Computing, GPGPU due to their data-intensive nature. As the num…
View article: Micro-Sector Cache
Micro-Sector Cache Open
Recent research proposals on DRAM caches with conventional allocation units (64 or 128 bytes) as well as large allocation units (512 bytes to 4KB) have explored ways to minimize the space/latency impact of the tag store and maximize the ef…