J. Ye
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View article: Research on damage identification method of aircraft panel structure based on fluctuation-based symbolic dynamics entropy
Research on damage identification method of aircraft panel structure based on fluctuation-based symbolic dynamics entropy Open
The panel structure is the main load-bearing component of core structures such as the aircraft fuselage and wing. In addition, as an important part of the aerodynamic shape, the smooth surface of the panel can significantly reduce flight r…
View article: Out of randomness: How evolution benefits from modularity
Out of randomness: How evolution benefits from modularity Open
Brute force random search, effective in exploring solution spaces, often becomes inefficient or infeasible in real-world scenarios with vast solution spaces. A more effective method, akin to natural evolution, involves recombining existing…
View article: Analysis and optimization of energy consumption characteristics for heating by nuclear power plants
Analysis and optimization of energy consumption characteristics for heating by nuclear power plants Open
View article: SAM-Net: Spatio-Temporal Sequence Typhoon Cloud Image Prediction Net with Self-Attention Memory
SAM-Net: Spatio-Temporal Sequence Typhoon Cloud Image Prediction Net with Self-Attention Memory Open
Cloud image prediction is a spatio-temporal sequence prediction task, similar to video prediction. Spatio-temporal sequence prediction involves learning from historical data and using the learned features to generate future images. In this…
View article: ETROC1: the first full chain precision timing prototype ASIC for CMS MTD endcap timing layer upgrade
ETROC1: the first full chain precision timing prototype ASIC for CMS MTD endcap timing layer upgrade Open
We present the design and characterization of the first full chain precision timing prototype ASIC, named ETL Readout Chip version 1 (ETROC1) for the CMS MTD endcap timing layer (ETL) upgrade. The ETL utilizes Low Gain Avalanche Diode (LGA…
View article: An FPGA-based readout chip emulator for the CMS ETL detector upgrade
An FPGA-based readout chip emulator for the CMS ETL detector upgrade Open
We present an FPGA-based readout chip emulator board for the CMS Endcap Timing Layer (ETL) detector upgrade. The emulator board uses an Intel Cyclone 10 GX FPGA to emulate the digital functions of four Endcap Layer Readout Chips (ETROCs). …
View article: An FPGA-based readout chip emulator for the CMS ETL detector upgrade
An FPGA-based readout chip emulator for the CMS ETL detector upgrade Open
We present an FPGA-based readout chip emulator board for the CMS Endcap Timing Layer (ETL) detector upgrade. The emulator board uses an Intel Cyclone 10 GX FPGA to emulate the digital functions of four Endcap Layer Readout Chips (ETROCs). …
View article: A prototype optical link board with redundancy design for the ATLAS\n liquid argon calorimeter Phase-2 upgrade
A prototype optical link board with redundancy design for the ATLAS\n liquid argon calorimeter Phase-2 upgrade Open
A prototype optical-link board has been developed for the ATLAS Liquid Argon\nCalorimeter Phase-2 upgrade. The board consists of 24 lpGBT chips and 8 VTRx+\nmodules and demonstrates the full optical link design of the future front-end\nboa…
View article: Characterization and quality control test of a gigabit cable receiver ASIC (GBCR2) for the ATLAS Inner Tracker Detector upgrade
Characterization and quality control test of a gigabit cable receiver ASIC (GBCR2) for the ATLAS Inner Tracker Detector upgrade Open
We present the characterization and quality control test of a gigabit cable\nreceiver ASIC prototype, GBCR2, for the ATLAS Inner Tracker pixel detector\nupgrade. GBCR2 equalizes and retimes the uplink electrical signals from RD53B\nthrough…
View article: Optical transceivers for event triggers in the ATLAS phase-I upgrade
Optical transceivers for event triggers in the ATLAS phase-I upgrade Open
View article: Prototyping of a 25 Gbps optical transmitter for applications in high-energy physics experiments
Prototyping of a 25 Gbps optical transmitter for applications in high-energy physics experiments Open
View article: Radiation testing campaign results for understanding the suitability of FPGAs in detector electronics
Radiation testing campaign results for understanding the suitability of FPGAs in detector electronics Open
View article: JTAG-based remote configuration of FPGAs over optical fibers
JTAG-based remote configuration of FPGAs over optical fibers Open
In this study, a remote FPGA-configuration method based on JTAG extension over optical fibers is presented. The method takes advantage of commercial components and ready-to-use software such as iMPACT and does not require any hardware or s…
View article: The VCSEL-based array optical transmitter (ATx) development towards 120-Gbps link for collider detector: development update
The VCSEL-based array optical transmitter (ATx) development towards 120-Gbps link for collider detector: development update Open
A compact radiation-tolerant array optical transmitter module (ATx) is\ndeveloped to provide data transmission up to 10Gbps per channel with 12\nparallel channels for collider detector applications. The ATx integrates a\nVertical Cavity Su…
View article: The clock distribution system for the ATLAS Liquid Argon Calorimeter Phase-I Upgrade Demonstrator
The clock distribution system for the ATLAS Liquid Argon Calorimeter Phase-I Upgrade Demonstrator Open
A prototype Liquid-argon Trigger Digitizer Board (LTDB), called the LTDB Demonstrator, has been developed to demonstrate the functions of the ATLAS Liquid Argon Calorimeter Phase-I trigger electronics upgrade. Forty Analog-to-Digital conve…