Jitendra Bhandari
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View article: ARIANNA: An Automatic Design Flow for Fabric Customization and eFPGA Redaction
ARIANNA: An Automatic Design Flow for Fabric Customization and eFPGA Redaction Open
In the modern global Integrated Circuit (IC) supply chain, protecting intellectual property (IP) is a complex challenge, and balancing IP loss risk and added cost for theft countermeasures is hard to achieve. Using embedded configurable lo…
View article: VeriLeaky: Navigating IP Protection vs Utility in Fine-Tuning for LLM-Driven Verilog Coding
VeriLeaky: Navigating IP Protection vs Utility in Fine-Tuning for LLM-Driven Verilog Coding Open
Large language models (LLMs) offer significant potential for coding, yet fine-tuning (FT) with curated data is essential for niche languages like Verilog. Using proprietary intellectual property (IP) for FT presents a serious risk, as FT d…
View article: RTL-Breaker: Assessing the Security of LLMs against Backdoor Attacks on HDL Code Generation
RTL-Breaker: Assessing the Security of LLMs against Backdoor Attacks on HDL Code Generation Open
Large language models (LLMs) have demonstrated remarkable potential with code generation/completion tasks for hardware design. In fact, LLM-based hardware description language (HDL) code generation has enabled the industry to realize compl…
View article: SENTAUR: Security EnhaNced Trojan Assessment Using LLMs Against Undesirable Revisions
SENTAUR: Security EnhaNced Trojan Assessment Using LLMs Against Undesirable Revisions Open
A globally distributed IC supply chain brings risks due to untrusted third parties. The risks span inadvertent use of hardware Trojan (HT), inserted Intellectual Property (3P-IP) or Electronic Design Automation (EDA) flows. HT can introduc…
View article: ASCENT: Amplifying Power Side-Channel Resilience via Learning & Monte-Carlo Tree Search
ASCENT: Amplifying Power Side-Channel Resilience via Learning & Monte-Carlo Tree Search Open
Power side-channel (PSC) analysis is pivotal for securing cryptographic hardware. Prior art focused on securing gate-level netlists obtained as-is from chip design automation, neglecting all the complexities and potential side-effects for …
View article: LLM-Aided Testbench Generation and Bug Detection for Finite-State Machines
LLM-Aided Testbench Generation and Bug Detection for Finite-State Machines Open
This work investigates the potential of tailoring Large Language Models (LLMs), specifically GPT3.5 and GPT4, for the domain of chip testing. A key aspect of chip design is functional testing, which relies on testbenches to evaluate the fu…
View article: Lightweight Countermeasures Against Static Power Side-Channel Attacks
Lightweight Countermeasures Against Static Power Side-Channel Attacks Open
This paper presents a novel defense strategy against static power side-channel attacks (PSCAs), a critical threat to cryptographic security. Our method is based on (1) carefully tuning high-Vth versus low-Vth cell selection during synthesi…
View article: Not All Fabrics Are Created Equal: Exploring eFPGA Parameters for IP Redaction
Not All Fabrics Are Created Equal: Exploring eFPGA Parameters for IP Redaction Open
Semiconductor design houses rely on third-party foundries to manufacture their integrated circuits (ICs). While this trend allows them to tackle fabrication costs, it introduces security concerns as external (and potentially malicious) par…
View article: ALICE
ALICE Open
Fabricating an integrated circuit is becoming unaffordable for many semiconductor design houses. Outsourcing the fabrication to a third-party foundry requires methods to protect the intellectual property of the hardware designs. Designers …
View article: Exploring eFPGA-based Redaction for IP Protection
Exploring eFPGA-based Redaction for IP Protection Open
Recently, eFPGA-based redaction has been proposed as a promising solution for hiding parts of a digital design from untrusted entities, where legitimate end-users can restore functionality by loading the withheld bitstream after fabricatio…
View article: Exploring eFPGA-based Redaction for IP Protection
Exploring eFPGA-based Redaction for IP Protection Open
Recently, eFPGA-based redaction has been proposed as a promising solution for hiding parts of a digital design from untrusted entities, where legitimate end-users can restore functionality by loading the withheld bitstream after fabricatio…