John Wickerson
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View article: Hardware.jl - An MLIR-based Julia HLS Flow (Work in Progress)
Hardware.jl - An MLIR-based Julia HLS Flow (Work in Progress) Open
Co-developing scientific algorithms and hardware accelerators requires domain-specific knowledge and large engineering resources. This leads to a slow development pace and high project complexity, which creates a barrier to entry that is t…
View article: Formalising CXL Cache Coherence
Formalising CXL Cache Coherence Open
We report our experience formally modelling and verifying CXL.cache, the inter-device cache coherence protocol of the Compute Express Link standard. We have used the Isabelle proof assistant to create a formal model for CXL.cache based on …
View article: Mix Testing: Specifying and Testing ABI Compatibility of C/C++ Atomics Implementations
Mix Testing: Specifying and Testing ABI Compatibility of C/C++ Atomics Implementations Open
The correctness of complex software depends on the correctness of both the source code and the compilers that generate corresponding binary code. Compilers must do more than preserve the semantics of a single source file: they must ensure …
View article: Hyperblock Scheduling for Verified High-Level Synthesis
Hyperblock Scheduling for Verified High-Level Synthesis Open
High-level synthesis (HLS) is the automatic compilation of software programs into custom hardware designs. With programmable hardware devices (such as FPGAs) now widespread, HLS is increasingly relied upon, but existing HLS tools are too u…
View article: Lost in Interpretation: Navigating Challenges in Validating Persistency Models Amid Vague Specs and Stubborn Machines, All with a Sense of Humour
Lost in Interpretation: Navigating Challenges in Validating Persistency Models Amid Vague Specs and Stubborn Machines, All with a Sense of Humour Open
Memory persistency models provide a foundation for persistent programming by specifying which (and when) writes to non-volatile memory (NVM) become persistent. Memory persistency models for the Intel-x86 and Arm architectures have been for…
View article: Validating Database System Isolation Level Implementations with Version Certificate Recovery
Validating Database System Isolation Level Implementations with Version Certificate Recovery Open
Transactions are a key feature of database systems and isolation levels specify the behavior of concurrently executing transactions. Ensuring their correct behavior is crucial. Recently, many isolation anomalies have been found in producti…
View article: Challenges in Empirically Testing Memory Persistency Models
Challenges in Empirically Testing Memory Persistency Models Open
Memory persistency models provide the foundational rules for software engineers to develop applications that take advantage of non-volatile memory (NVM), dictating which (and when) writes to NVM are deemed persistent. Though formalised for…
View article: Artifact Report: Intel PMDK Transactions: Specification, Validation and Concurrency
Artifact Report: Intel PMDK Transactions: Specification, Validation and Concurrency Open
This report extends §6 of the main paper by providing further details of the mechanisation effort.
View article: Intel PMDK Transactions: Specification, Validation and Concurrency
Intel PMDK Transactions: Specification, Validation and Concurrency Open
Software Transactional Memory (STM) is an extensively studied paradigm that provides an easy-to-use mechanism for thread safety and concurrency control. With the recent advent of byte-addressable persistent memory, a natural question to as…
View article: Artifact for "Challenges in Empirically Testing Memory Persistency Models"
Artifact for "Challenges in Empirically Testing Memory Persistency Models" Open
Here, we provide the litmus tests, auxiliary scripts, and output data comprising the artifact accompanying the paper titled 'Challenges in Empirically Testing Memory Persistency Models', published in ICSE NIER'24.
View article: Artifact for "Challenges in Empirically Testing Memory Persistency Models"
Artifact for "Challenges in Empirically Testing Memory Persistency Models" Open
Presented here are the litmus tests, auxiliary scripts, and output data constituting the artifact accompanying the paper titled 'Challenges in Empirically Testing Memory Persistency Models,' published in ICSE NIER'24. For detailed informat…
View article: Artifact for "Challenges in Empirically Testing Memory Persistency Models"
Artifact for "Challenges in Empirically Testing Memory Persistency Models" Open
Presented here are the litmus tests, auxiliary scripts, and output data constituting the artifact accompanying the paper titled 'Challenges in Empirically Testing Memory Persistency Models,' published in ICSE NIER'24. For detailed informat…
View article: Intel PMDK Transactions: Specification, Validation and Concurrency (Extended Version)
Intel PMDK Transactions: Specification, Validation and Concurrency (Extended Version) Open
Software Transactional Memory (STM) is an extensively studied paradigm that provides an easy-to-use mechanism for thread safety and concurrency control. With the recent advent of byte-addressable persistent memory, a natural question to as…
View article: Simulating Operational Memory Models Using Off-the-Shelf Program Analysis Tools
Simulating Operational Memory Models Using Off-the-Shelf Program Analysis Tools Open
Memory models allow reasoning about the correctness of multithreaded programs. Constructing and using such models is facilitated by simulators that reveal which behaviours of a given program are allowed. While extensive work has been done …
View article: Balancing Static Islands in Dynamically Scheduled Circuits Using Continuous Petri Nets
Balancing Static Islands in Dynamically Scheduled Circuits Using Continuous Petri Nets Open
High-level synthesis (HLS) tools automatically transform a high-level program, for example in C/C++, into a low-level hardware description. A key challenge in HLS is scheduling, i.e. determining the start time of all the operations in the …
View article: Parallelising Control Flow in Dynamic-scheduling High-level Synthesis
Parallelising Control Flow in Dynamic-scheduling High-level Synthesis Open
Recently, there is a trend to use high-level synthesis (HLS) tools to generate dynamically scheduled hardware. The generated hardware is made up of components connected using handshake signals. These handshake signals schedule the componen…
View article: Taking Back Control in an Intermediate Representation for GPU Computing
Taking Back Control in an Intermediate Representation for GPU Computing Open
We describe our experiences successfully applying lightweight formal methods to substantially improve and reformulate an important part of Standard Portable Intermediate Representation SPIRV, an industry-standard language for GPU computing…
View article: High‐coverage metamorphic testing of concurrency support in C compilers
High‐coverage metamorphic testing of concurrency support in C compilers Open
Summary We present a technique and automated toolbox for randomized testing of C compilers. Unlike prior compiler‐testing approaches, we generate concurrent test cases in which threads communicate using fine‐grained atomic operations, and …
View article: View-Based Owicki-Gries Reasoning for Persistent x86-TSO (Extended Version)
View-Based Owicki-Gries Reasoning for Persistent x86-TSO (Extended Version) Open
The rise of persistent memory is disrupting computing to its core. Our work aims to help programmers navigate this brave new world by providing a program logic for reasoning about x86 code that uses low-level operations such as memory acce…
View article: View-Based Owicki–Gries Reasoning for Persistent x86-TSO
View-Based Owicki–Gries Reasoning for Persistent x86-TSO Open
The rise of persistent memory is disrupting computing to its core. Our work aims to help programmers navigate this brave new world by providing a program logic for reasoning about x86 code that uses low-level operations such as memory acce…
View article: The semantics of shared memory in Intel CPU/FPGA systems
The semantics of shared memory in Intel CPU/FPGA systems Open
Heterogeneous CPU/FPGA devices, in which a CPU and an FPGA can execute together while sharing memory, are becoming popular in several computing sectors. In this paper, we study the shared-memory semantics of these devices, with a view to p…
View article: Specifying and testing GPU workgroup progress models
Specifying and testing GPU workgroup progress models Open
As GPU availability has increased and programming support has matured, a wider variety of applications are being ported to these platforms. Many parallel applications contain fine-grained synchronization idioms; as such, their correct exec…
View article: Formal verification of high-level synthesis
Formal verification of high-level synthesis Open
High-level synthesis (HLS), which refers to the automatic compilation of software into hardware, is rapidly gaining popularity. In a world increasingly reliant on application-specific hardware accelerators, HLS promises hardware designs of…
View article: Efficient Memory Arbitration in High-Level Synthesis From Multi-Threaded Code
Efficient Memory Arbitration in High-Level Synthesis From Multi-Threaded Code Open
High-level synthesis (HLS) is an increasingly popular method for generating hardware from a description written in a software language like C/C++. Traditionally, HLS tools have operated on sequential code, however in recent years there has…
View article: DASS: Combining Dynamic & Static Scheduling in High-Level Synthesis
DASS: Combining Dynamic & Static Scheduling in High-Level Synthesis Open
A central task in high-level synthesis is scheduling: the allocation of operations to clock cycles. The classic approach to scheduling is static, in which each operation is mapped to a clock cycle at compile-time, but recent years have see…
View article: Precise Pointer Analysis in High-Level Synthesis
Precise Pointer Analysis in High-Level Synthesis Open
Pointer analysis computes the set of memory locations that each pointer access can point to during hardware runtime. The more sensitive the pointer analysis, the more precise these sets are likely to be, reducing unnecessary sharing of mem…
View article: Combining Dynamic & Static Scheduling in High-level Synthesis
Combining Dynamic & Static Scheduling in High-level Synthesis Open
A central task in high-level synthesis isscheduling: the allocationof operations to clock cycles. The classic approach to schedulingisstatic, in which each operation is mapped to a clock cycle atcompile-time, but recent years have seen the…