Jongwook Jeon
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View article: Photonic Modulation of Negative Differential Transconductance for Tunable Multivalued Logic in Heterojunction Transistors
Photonic Modulation of Negative Differential Transconductance for Tunable Multivalued Logic in Heterojunction Transistors Open
Logic conversion within multivalued logic (MVL) circuits is a promising solution that enhances complex data processing achieved through the modulation of negative differential transconductance (NDT) characteristics of heterojunction transi…
View article: A Comparative Analysis of Middle-of-Line Contact Architectures for Complementary FETs
A Comparative Analysis of Middle-of-Line Contact Architectures for Complementary FETs Open
In this paper, we have investigated various middle-of-line contact architectures applied to monolithic complementary FET inverters and have performed a comparative analysis to assess their respective advantages and limitations. For each sc…
View article: Efficacy and safety of choline alphoscerate for amnestic mild cognitive impairment: a randomized double-blind placebo-controlled trial
Efficacy and safety of choline alphoscerate for amnestic mild cognitive impairment: a randomized double-blind placebo-controlled trial Open
Background Effective interventions for overall healthy subjects with mild cognitive impairment are currently limited. Choline alphoscerate (alpha glyceryl phosphorylcholine, αGPC) is a choline-containing phospholipid used to treat cognitiv…
View article: Analyzing Various Structural and Temperature Characteristics of Floating Gate Field Effect Transistors Applicable to Fine-Grain Logic-in-Memory Devices
Analyzing Various Structural and Temperature Characteristics of Floating Gate Field Effect Transistors Applicable to Fine-Grain Logic-in-Memory Devices Open
Although the von Neumann architecture-based computing system has been used for a long time, its limitations in data processing, energy consumption, etc. have led to research on various devices and circuit systems suitable for logic-in-memo…
View article: High‐<i>κ</i> Dielectric (HfO<sub>2</sub>)/2D Semiconductor (HfSe<sub>2</sub>) Gate Stack for Low‐Power Steep‐Switching Computing Devices
High‐<i>κ</i> Dielectric (HfO<sub>2</sub>)/2D Semiconductor (HfSe<sub>2</sub>) Gate Stack for Low‐Power Steep‐Switching Computing Devices Open
Herein, a high‐quality gate stack (native HfO 2 formed on 2D HfSe 2 ) fabricated via plasma oxidation is reported, realizing an atomically sharp interface with a suppressed interface trap density ( D it ≈ 5 × 10 10 cm −2 eV −1 ). The chemi…
View article: Large-Scale Training in Neural Compact Models for Accurate and Adaptable MOSFET Simulation
Large-Scale Training in Neural Compact Models for Accurate and Adaptable MOSFET Simulation Open
We address the challenges associated with traditional analytical models, such as BSIM, in semiconductor device modeling. These models often face limitations in accurately representing the complex behaviors of miniaturized devices. As an al…
View article: Seamless monolithic three-dimensional integration of single-crystalline films by growth
Seamless monolithic three-dimensional integration of single-crystalline films by growth Open
The demand for the three-dimensional (3D) integration of electronic components is on a steady rise. The through-silicon-via (TSV) technique emerges as the only viable method for integrating single-crystalline device components in a 3D form…
View article: Efficacy and Safety of Choline Alphoscerate for Amnestic Mild Cognitive Impairment: A Randomized Double-Blind Placebo-Controlled Trial
Efficacy and Safety of Choline Alphoscerate for Amnestic Mild Cognitive Impairment: A Randomized Double-Blind Placebo-Controlled Trial Open
Background Effective interventions for overall healthy subjects with mild cognitive impairment are currently limited. Choline alphoscerate (alpha glyceryl phosphorylcholine, αGPC) is a choline-containing phospholipid used to treat cognitiv…
View article: Circuit simulation of floating-gate FET (FGFET) for logic application
Circuit simulation of floating-gate FET (FGFET) for logic application Open
In this study, a floating-gate field-effect transistor (FGFET) structure is proposed and verified through simulations. Current memory devices often rely on the von Neumann architecture which suffers from von Neumann bottleneck. The propose…
View article: Investigation on floating-gate field-effect transistor for logic-in-memory application
Investigation on floating-gate field-effect transistor for logic-in-memory application Open
In this paper, we present analysis results on the applicability of a previously introduced memory device, floating-gate field-effect transistor (FGFET), to a logic-in-memory (LiM) system for the first time. Device optimization and compact …
View article: Modulation of Contact Resistance of Dual‐Gated MoS<sub>2</sub> FETs Using Fermi‐Level Pinning‐Free Antimony Semi‐Metal Contacts
Modulation of Contact Resistance of Dual‐Gated MoS<sub>2</sub> FETs Using Fermi‐Level Pinning‐Free Antimony Semi‐Metal Contacts Open
Achieving low contact resistance ( R C ) is one of the major challenges in producing 2D FETs for future CMOS technology applications. In this work, the electrical characteristics for semimetal (Sb) and normal metal (Ti) contacted MoS 2 dev…
View article: Self-Heating and Corner Rounding Effects on Time Dependent Dielectric Breakdown of Stacked Multi-Nanosheet FETs
Self-Heating and Corner Rounding Effects on Time Dependent Dielectric Breakdown of Stacked Multi-Nanosheet FETs Open
In this work, by employing the developed kinetic Monte Carlo (kMC)-based time-dependent dielectric breakdown (TDDB) analysis simulator, the lifetime characteristics change by TDDB in the stacked multi-nanosheet field-effect transistor (mNS…
View article: Analysis of Logic-in-Memory Full Adder Circuit With Floating Gate Field Effect Transistor (FGFET)
Analysis of Logic-in-Memory Full Adder Circuit With Floating Gate Field Effect Transistor (FGFET) Open
The high data throughput and high energy efficiency required recently are increasingly difficult to implement due to the von Neumann bottleneck. As a way to overcome this, Logic-in-Memory (LiM) technology has recently been receiving a lot …
View article: Accurate Layout-Dependent Effect Model in 10 nm-Class DRAM Process Using Area-Efficient Array Test Circuits
Accurate Layout-Dependent Effect Model in 10 nm-Class DRAM Process Using Area-Efficient Array Test Circuits Open
This study presents an accurate model for non-monotonic layout-dependent effects (LDEs) measured using 10nm-class dynamic random access memory technology. To collect the LDE measurement data, a test module with an individually addressable …
View article: Device and Circuit Analysis of Double Gate Field Effect Transistor with Mono-Layer WS2-Channel at Sub-2 nm Technology Node
Device and Circuit Analysis of Double Gate Field Effect Transistor with Mono-Layer WS2-Channel at Sub-2 nm Technology Node Open
In this work, WS2 was adopted as a channel material among transition metal dichalcogenides (TMD) materials that have recently been in the spotlight, and the circuit power performance (power consumption, operating frequency) of the monolaye…
View article: Optimization of Gate-All-Around Device to Achieve High Performance and Low Power with Low Substrate Leakage
Optimization of Gate-All-Around Device to Achieve High Performance and Low Power with Low Substrate Leakage Open
In this study on multi-nanosheet field-effect transistor (mNS-FET)—one of the gate-all-around FETs (GAAFET) in the 3 nm technology node dimension—3D TCAD (technology computer-aided design) was used to attain optimally reduced substrate lea…
View article: Investigation on the Effects of Interconnect RC in 3nm Technology Node Using Path-Finding Process Design Kit
Investigation on the Effects of Interconnect RC in 3nm Technology Node Using Path-Finding Process Design Kit Open
With the continuous development of front-end-of-line (FEOL) technology, the development of interconnection processes at nanoscale process nodes is becoming important. We conducted a post-layout circuit simulation to consider the effect of …
View article: Analytical Current–Voltage Modeling and Analysis of the MFIS Gate-All-Around Transistor Featuring Negative-Capacitance
Analytical Current–Voltage Modeling and Analysis of the MFIS Gate-All-Around Transistor Featuring Negative-Capacitance Open
Recently, in accordance with the demand for development of low-power semiconductor devices, a negative capacitance field-effect-transistor (NC-FET) that integrates ferroelectric material into a gate stack and utilizes negative capacitive b…
View article: Device and Circuit Exploration of Multi-Nanosheet Transistor for Sub-3 nm Technology Node
Device and Circuit Exploration of Multi-Nanosheet Transistor for Sub-3 nm Technology Node Open
A multi-nanosheet field-effect transistor (mNS-FET) device was developed to maximize gate controllability while making the channel in the form of a sheet. The mNS-FET has superior gate controllability for the stacked channels; consequently…
View article: Correction to “Characteristic Length of Macaroni Channel MOSFET” [Nov 19 1720-1723]
Correction to “Characteristic Length of Macaroni Channel MOSFET” [Nov 19 1720-1723] Open
In the above letter [1] , we would like to modify the authors’ affiliations as follows:
View article: Alpha Particle Effect on Multi-Nanosheet Tunneling Field-Effect Transistor at 3-nm Technology Node
Alpha Particle Effect on Multi-Nanosheet Tunneling Field-Effect Transistor at 3-nm Technology Node Open
The radiation effects on a multi-nanosheet tunneling-based field effect transistor (NS-TFET) were investigated for a 3-nm technology node using a three-dimensional (3D) technology computer-aided design (TCAD) simulator. An alpha particle w…
View article: Analytical Current-Voltage Model for Gate-All-Around Transistor with Poly-Crystalline Silicon Channel
Analytical Current-Voltage Model for Gate-All-Around Transistor with Poly-Crystalline Silicon Channel Open
Poly-crystalline silicon channel transistors have been used as a display TFT for a long time and have recently been used in a 3D vertical NAND Flash which is a transistor with 2D plane NAND upright. In addition, multi-gate transistors such…
View article: Development of an Advanced TDDB Analysis Model for Temperature Dependency
Development of an Advanced TDDB Analysis Model for Temperature Dependency Open
This paper proposes a hybrid model to describe the temperature dependence of the time-dependent dielectric breakdown (TDDB) phenomenon. TDDB can be expressed in terms of two well-known representative degradation mechanisms: The thermo-chem…
View article: Erratum for: Design optimization of RF low noise amplifier in twin‐well CMOS process
Erratum for: Design optimization of RF low noise amplifier in twin‐well CMOS process Open
In the above-mentioned article, which appeared in Microwave and Optical Technology Letters, Volume 59#12, DOI 30895, author Myounggon Kang's name was published incorrectly. Below is his corrected name. Hee-Sauk Jhon1 | Jongwook Jeon2 | Myo…
View article: Erratum for: Noise Figure Improvement by Controlling Wiring Effects in RF Low Noise Amplifiers
Erratum for: Noise Figure Improvement by Controlling Wiring Effects in RF Low Noise Amplifiers Open
Received 31 October 2016 In the above-mentioned article, which appeared in Microwave and Optical Technology Letters, Volume 59#6, DOI 30555, author Myunggon Kang's name was published incorrectly. His correct name is shown below: Hee-Sauk J…
View article: Development of Organic Semiconductors Based on Quinacridone Derivatives for Organic Field-Effect Transistors: High-Voltage Logic Circuit Applications
Development of Organic Semiconductors Based on Quinacridone Derivatives for Organic Field-Effect Transistors: High-Voltage Logic Circuit Applications Open
Poly[quinacridone-alt-quaterthiophene] (PQCQT) was synthesized, using a Suzuki coupling reaction, to investigate the potential of quinacridone derivatives as organic semiconductors in organic fieldeffect transistors (OFETs) and circuits. A…