Explanipedia

Low-frequency noise characteristics of waveguide-integrated lateral and vertical Ge-on-Si p–i–n photodiodes Open

Solomon Musibau, Kellen P. Arnold, Veluri Anurag Reddy, J. Franco, Artemisia Tsiara , et al. · 2025

We report forward bias and temperature-dependent low-frequency (LF) noise characteristics of waveguide-integrated Ge-on-Si p–i–n photodiodes across three architectures: doped-Si lateral, doped-Ge and doped-Si lateral, and vertical heteroju…

Characterization of Extended Gamma-Ray Sources with SWGO: Morphological Models and Detection Techniques. Open

Erick Alejandro Rangel Anita, J. Franco, M. M. González · 2025

Molecularly defined auditory neuron subtypes show different vulnerabilities to noise- and age-related synaptopathy in mice Open

Lisa V. Goodrich, J. Franco, Taylor Copeland, Ryan Merrow · 2025

Neuronal subtype-specific synaptopathy is a hallmark of many forms of neurodegeneration. We examined the cellular basis for synaptic vulnerability in the auditory system, where three subtypes of spiral ganglion neurons (SGNs)—Ia, Ib, and I…

Positive Bias Temperature Instability (PBTI) in n- and p-Channel Polysilicon Thin-Film Transistors (TFTs) for High-Voltage Applications Open

Ben Kaczer, Seyed Mojtaba Sadati Faramarzi, Luca Panarella, François Berghmans, J. Franco , et al. · 2025

Characterization of DC performance and low-frequency noise of an array of nMOS Forksheets from 300 K to 4 K Open

R. Asanovski, Alexander Grill, J. Franco, Pierpaolo Palestri, Hans Mertens , et al. · 2024

The DC and low-frequency noise performance of an array of 800 parallel Forksheet MOSFETs were investigated by performing measurements over a wide temperature range from 300 K to 4 K. The array structure allowed to measure a representative …

Characterization and Advanced Modeling of Dielectric Defects in Low-Thermal Budget RMG MOSFETs Using 1/f Noise Analysis Open

R. Asanovski, Hiroaki Arimura, Jean‐François de Marneffe, Pierpaolo Palestri, Naoto Horiguchi , et al. · 2024

This study presents a comprehensive investigation of defects in the gate-stack of low-thermal budget replacement metal gate (RMG) MOSFETs treated with novel dielectric passivation techniques using 1/ f noise characterization and advanc…

Probing Band Tail States in MOSFETs at Cryogenic Temperatures through Noise Spectroscopy Open

R. Asanovski, Alexander Grill, J. Franco, Pierpaolo Palestri, Ruoyu Li , et al. · 2023

Investigating the correlation between interface and dielectric trap densities in aged p-MOSFETs using current-voltage, charge pumping, and 1/f noise characterization techniques Open

R. Asanovski, J. Franco, Pierpaolo Palestri, B. Kaczer, L. Selmi · 2023

Comphy v3.0—A compact-physics framework for modeling charge trapping related reliability phenomena in MOS devices Open

Dominic Waldhoer, Christian Schleich, Jakob Michl, Alexander Grill, D. Claes , et al. · 2023

Charge trapping plays an important role for the reliability of electronic devices and manifests itself in various phenomena like bias temperature instability (BTI), random telegraph noise (RTN), hysteresis or trap-assisted tunneling (TAT).…

Understanding the Excess 1/f Noise in MOSFETs at Cryogenic Temperatures Open

R. Asanovski, Alexander Grill, J. Franco, Pierpaolo Palestri, Arnout Beckers , et al. · 2023

Characterization, modeling, and development of cryo-temperature CMOS technologies (cryo-CMOS) have significantly progressed to help overcome the interconnection bottleneck between qubits and the readout interface in quantum computers. Neve…

Hot-Carrier Induced Degradation of Ge/Sti Interfaces in Ge-on-Si Junction Devices Open

Solomon Musibau, J. Franco, Artemisia Tsiara, Ingrid De Wolf, Kristof Croes · 2023

A Pragmatic Model to Predict Future Device Aging Open

James Brown, Kean Hong Tok, Rui Gao, Zhigang Ji, Weidong Zhang , et al. · 2023

To predict long term device aging under use bias, models extracted from voltage accelerated tests must be extrapolated into the future. The traditional model uses a power law, to linearly fit the test data on a log-log plot, and then extra…

Comphy v3.0 -- A Compact-Physics Framework for Modeling Charge Trapping Related Reliability Phenomena in MOS Devices Open

Dominic Waldhoer, Christian Schleich, Jakob Michl, Alexander Grill, D. Claes , et al. · 2022

Charge trapping plays an important role for the reliability of electronic devices and manifests itself in various phenomena like bias temperature instability (BTI), random telegraph noise (RTN), hysteresis or trap-assisted tunneling (TAT).…

New insights on the excess 1/f noise at cryogenic temperatures in 28 nm CMOS and Ge MOSFETs for quantum computing applications Open

R. Asanovski, Alexander Grill, J. Franco, Pierpaolo Palestri, Arnout Beckers , et al. · 2022

Cryo-CMOS characterization, modeling, and development have significantly progressed to help overcome the interconnection bottleneck between qubits and the readout interface of quantum computers. Nevertheless, available compact models for c…

Harnessing charge injection in Kelvin probe force microscopy for the evaluation of oxides Open

Umberto Celano, Y. Lee, Jill Serron, Christina H. Smith, J. Franco , et al. · 2021

On The Development of a Reliable Gate Stack for Future Technology Nodes Based on III-V Materials Open

Abhitosh Vais, Sonja Sioncke, J. Franco, V. Putcha, Laura Nyns , et al. · 2018

In this work, we discuss how the insertion of a LaSiOx layer in between an in-house IL passivation layer and the high-k has moved the III-V gate stack into the target window for future technology nodes.The insertion of this LaSiOx layer in…

Физические основы самосогласованного моделирования процессов генерации интерфейсных состояний и транспорта горячих носителей в транзисторах на базе структур металл-диэлектрик-кремний Open

С.Э. Тягинов, Alexander Makarov, Markus Jech, М.И. Векслер, J. Franco , et al. · 2018

A detailed simulation of degradation (caused by hot charge carriers) based on self-consistent consideration of the transport of charge carriers and the generation of defects at the SiO_2/Si interface is carried out for the first time. The …

NBTI-Generated Defects in Nanoscaled Devices: Fast Characterization Methodology and Modeling Open

Rui Gao, Zhigang Ji, Azrif Manut, J. F. Zhang, J. Franco , et al. · 2017

Negative bias temperature instability (NBTI)-generated defects (GDs) have been widely observed and known to play an important role in device’s lifetime. However, its characterization and modeling in nanoscaled devices is a challenge due to…

High Mobility In0.53Ga0.47As MOSFETs With Steep Sub-Threshold Slope Achieved by Remote Reduction of Native III-V Oxides With Metal Electrodes Open

Shinichi Yoshida, Nadine Collaert, H. Watanabe, Aaron Thean, H. C. Lin , et al. · 2017

We have validated that the electrical performances of the In_0.53Ga_0.47As MOSFETs such as sub-threshold slope (SS) and electron mobility were dependent on interfacial reactions in the metal/highk/InGaAs gate stacks whi…

Understanding charge traps for optimizing Si-passivated Ge nMOSFETs Open

Pengpeng Ren, Rui Gao, Zhigang Ji, Hiroaki Arimura, J. F. Zhang , et al. · 2016

Ge is an attractive channel material offering high hole and electron mobility, and therefore of interest for future p- and n-FET technologies. Ge nFETs can be made through two routes: GeO2/high-k directly on Ge [1] or using a Si-passivated…

An Investigation on Border Traps in III–V MOSFETs With an In0.53Ga0.47As Channel Open

Zhigang Ji, Xiong Zhang, J. Franco, Rui Gao, Meng Duan , et al. · 2015

© 2015 IEEE. Continuing CMOS performance scaling requires developing MOSFETs of high-mobility semiconductors and InGaAs is a strong candidate for n-channel. InGaAs MOSFETs, however, suffer from high densities of border traps, and their ori…

Correlation of interface states/border traps and threshold voltage shift on AlGaN/GaN metal-insulator-semiconductor high-electron-mobility transistors Open

Tian‐Li Wu, Denis Marcon, Benoit Bakeroot, Brice De Jaeger, H. C. Lin , et al. · 2015

In this paper, three electrical techniques (frequency dependent conductance analysis, AC transconductance (AC-gm), and positive gate bias stress) were used to evaluate three different gate dielectrics (Plasma-Enhanced Atomic Layer Depositi…

2014 IRPS Paper Awards to be Recognized at 2015 IRPS [6 awards] Open

Angela Oates, M.H. Lin, Tibor Grasser, K. Rott, H. Reisinger , et al. · 2015

Origins and implications of increased channel hot carrier variability in nFinFETs Open

B. Kaczer, J. Franco, M. Cho, Tibor Grasser, Ph. J. Roussel , et al. · 2015

Channel hot carrier (CHC) stress is observed to result in higher variability of degradation in deeply-scaled nFinFETs than bias temperature instability (BTI) stress. Potential sources of this increased variation are discussed and the intri…

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