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View article: Scalable Sequential Optimization Under Observability Don't Cares
Scalable Sequential Optimization Under Observability Don't Cares Open
Sequential logic synthesis can provide better Power-Performance-Area (PPA) than combinational logic synthesis since it explores a larger solution space. As the gate cost in advanced technologies keeps rising, sequential logic synthesis pro…
View article: Improving LUT-based optimization for ASICs
Improving LUT-based optimization for ASICs Open
LUT-based optimization techniques are finding new applications in synthesis of ASIC designs. Intuitively, packing logic into LUTs provides a better balance between functionality and structure in logic optimization. On this basis, the LUT-e…
View article: Majority-based Design Flow for AQFP Superconducting Family
Majority-based Design Flow for AQFP Superconducting Family Open
Adiabatic superconducting devices are promising candidates to develop high-speed/low-power electronics. Advances in physical technology must be matched with a systematic development of comprehensive design and simulation tools to bring sup…
View article: LUT-Based Optimization For ASIC Design Flow
LUT-Based Optimization For ASIC Design Flow Open
In this paper, we develop a new LUT-based optimization flow tailored for the synthesis of ASICs rather than FPGAs. We enhance LUT-mapping to consider the literal/AIG cost of LUT-nodes. We extend traditional Boolean methods to simplify and …
View article: Read your Circuit
Read your Circuit Open
To tackle the involved complexity, Electronic Design Automation (EDA) tools are broken in well-defined steps, each operating at different abstraction levels. Higher levels of abstraction shorten the flow run-time while sacrificing correlat…
View article: SAT-Sweeping Enhanced for Logic Synthesis
SAT-Sweeping Enhanced for Logic Synthesis Open
SAT-sweeping is a powerful method for simplifying logic networks. It consists of merging gates that are proven equivalent (up to complementation) by running simulation and SAT solving in synergy. SAT-sweeping is used in both verification a…
View article: A Logic Synthesis Toolbox for Reducing the Multiplicative Complexity in Logic Networks
A Logic Synthesis Toolbox for Reducing the Multiplicative Complexity in Logic Networks Open
Logic synthesis is a fundamental step in the realization of modern integrated circuits. It has traditionally been employed for the optimization of CMOS-based designs, as well as for emerging technologies and quantum computing. Recently, it…
View article: Extending Boolean Methods for Scalable Logic Synthesis
Extending Boolean Methods for Scalable Logic Synthesis Open
In recent years, Boolean methods in logic synthesis have been drawing the attention of EDA researchers due to the continuous push to advance quality of results. Boolean methods require high computational cost, as they rely on complete func…
View article: Reducing the Multiplicative Complexity in Logic Networks for Cryptography and Security Applications
Reducing the Multiplicative Complexity in Logic Networks for Cryptography and Security Applications Open
Reducing the number of AND gates plays a central role in many cryptography and security applications. We propose a logic synthesis algorithm and tool to minimize the number of AND gates in a logic network composed of AND, XOR, and inverter…
View article: Scalable Generic Logic Synthesis
Scalable Generic Logic Synthesis Open
This paper proposes a novel methodology for multi-level logic synthesis that is independent from a specific graph data-structure, but formulates synthesis procedures using an abstract concept definition of a logic representation. The idea …
View article: Scalable Boolean Methods in a Modern Synthesis Flow
Scalable Boolean Methods in a Modern Synthesis Flow Open
With the continuous push to improve Quality of Results (QoR) in EDA, Boolean methods in logic synthesis have been recently drawing the attention of researchers. Boolean methods achieve better QoR than algebraic methods but require higher c…
View article: The EPFL Combinational Benchmark Suite
The EPFL Combinational Benchmark Suite Open
The EPFL Combinational Benchmark Suite was introduced in 2015 with the aim of defining a new comparative standard for the logic optimization and synthesis community. It originally consisted of 23 combinational circuits designed to challeng…
View article: Integrated ESOP Refactoring for Industrial Designs
Integrated ESOP Refactoring for Industrial Designs Open
We present a multi-level logic refactoring algorithm based on exclusive sum-of-product (ESOP) expressions. ESOP expressions are two-level logic representation forms, similar to sum of -product (SOP) expressions. However, ESOPs use EXOR ins…
View article: Mapping Monotone Boolean Functions into Majority
Mapping Monotone Boolean Functions into Majority Open
We consider the problem of decomposing monotone Boolean functions into majority-of-three operations, with a particular focus on decomposing the majority-n function. When targeting monotone Boolean functions, Shannon's expansion can be expr…
View article: Majority logic synthesis
Majority logic synthesis Open
The majority function (xyz) evaluates to true, if at least two of its Boolean inputs evaluate to true. The majority function has frequently been studied as a central primitive in logic synthesis applications for many decades. Knuth refers …
View article: Size Optimization of MIGs with an Application to QCA and STMG Technologies
Size Optimization of MIGs with an Application to QCA and STMG Technologies Open
Majority-inverter graphs (MIGs) are a logic representation with remarkable algebraic and Boolean properties that enable efficient logic optimizations beyond the capabilities of traditional logic representations. Further, since many nano-em…
View article: Practical exact synthesis
Practical exact synthesis Open
In this paper, we discuss recent advances in exact synthesis, considering both their efficient implementation and various applications in which they can he employed. We emphasize on solving exact synthesis through Boolean satisfiability (S…
View article: Improvements to boolean resynthesis
Improvements to boolean resynthesis Open
In electronic design automation Boolean resynthesis techniques are increasingly used to improve the quality of results where algebraic methods hit local minima Boolean methods rely on complete functional properties of a logic circuit, pref…
View article: Enabling exact delay synthesis
Enabling exact delay synthesis Open
Given (i) a Boolean function, (ii) a set of arrival times at the inputs, and (iii) a gate library with associated delay values, the exact delay synthesis problem asks for a circuit implementation which minimizes the arrival time at the out…
View article: Improving Circuit Mapping Performance Through MIG-based Synthesis for Carry Chains
Improving Circuit Mapping Performance Through MIG-based Synthesis for Carry Chains Open
Hard-wired carry chains in FPGAs are designed to improve efficiency of important arithmetic primitives. Although they are proven to be effective for arithmetic-rich functions, there are very few studies on the optimization opportunities of…
View article: Wave pipelining for majority-based beyond-CMOS technologies
Wave pipelining for majority-based beyond-CMOS technologies Open
The performance of some emerging nanotechnolo- gies benefits from wave pipelining. The design of such circuits re- quires new models and algorithms. Thus we show how Majority- Inverter Graphs (MIG) can be used for this purpose and we exten…
View article: Exact Synthesis of Majority-Inverter Graphs and Its Applications
Exact Synthesis of Majority-Inverter Graphs and Its Applications Open
We propose effective algorithms for exact synthesis of Boolean logic networks using satisfiability modulo theories (SMT) solvers. Since exact synthesis is a difficult problem, it can only be applied efficiently to very small functions, hav…
View article: Multi-level logic benchmarks: An exactness study
Multi-level logic benchmarks: An exactness study Open
In this paper, we study exact multi-level logic benchmarks. We refer to an exact logic benchmark, or exact benchmark in short, as the optimal implementation of a given Boolean function, in terms of minimum number of logic levels and/or nod…
View article: A novel basis for logic rewriting
A novel basis for logic rewriting Open
Given a set of logic primitives and a Boolean function, exact synthesis finds the optimum representation (e.g., depth or size) of the function in terms of the primitives. Due to its high computational complexity, the use of exact synthesis…
View article: Inversion optimization in majority-inverter graphs
Inversion optimization in majority-inverter graphs Open
Many emerging nanotechnologies realize majority gates as primitive building blocks and they benefit from a majority-based synthesis. Recently, Majority-Inverter Graphs (MIGs) have been introduced to abstract these new technologies. We pres…
View article: LUT Mapping and Optimization for Majority-Inverter Graphs
LUT Mapping and Optimization for Majority-Inverter Graphs Open
A Majority-Inverter Graph (MIG) is a directed acyclic graph in which every vertex represents a three-input majority operation and edges may be complemented to indicate operand inversion. MIGs have algebraic and Boolean properties that enab…
View article: An MIG-based compiler for programmable logic-in-memory architectures
An MIG-based compiler for programmable logic-in-memory architectures Open
Resistive memories have gained high research attention for enabling design of in-memory computing circuits and systems. We propose for the first time an automatic compilation methodology suited to a recently proposed computer architecture …