Lukáš Kohútka
YOU?
Author Swipe
View article: Lockstep Replacement: Fault-Tolerant Design
Lockstep Replacement: Fault-Tolerant Design Open
System-level lockstep, interconnecting two original cores, is nowadays the state-of-the-art approach for protecting processor systems against random hardware faults. However, the lack of information outside the cores necessitates many comp…
View article: On-Chip Bus Protection against Soft Errors
On-Chip Bus Protection against Soft Errors Open
The increasing performance demands for processors leveraged in mission and safety-critical applications mean that the processors are implemented in smaller fabrication technologies, allowing a denser integration and higher operational freq…
View article: In-Pipeline Processor Protection against Soft Errors
In-Pipeline Processor Protection against Soft Errors Open
The shrinking of technology nodes allows higher performance, but susceptibility to soft errors increases. The protection has been implemented mainly by lockstep or hardened process techniques, which results in a lower frequency, a larger a…
View article: A New FPGA-Based Task Scheduler for Real-Time Systems
A New FPGA-Based Task Scheduler for Real-Time Systems Open
This research demonstrates a novel design of an FPGA-implemented task scheduler for real-time systems that supports both aperiodic and periodic tasks. The periodic tasks are automatically restarted once their period has expired without any…
View article: A New FPGA-based Architecture of Task Scheduler with Support of Periodic Real-Time Tasks
A New FPGA-based Architecture of Task Scheduler with Support of Periodic Real-Time Tasks Open
This paper presents a new FPGA design of a task scheduler that supports not only aperiodic hard real-time tasks but periodic tasks too. Whenever a period of a periodic task is elapsed, the task is automatically restarted with no need of so…
View article: Efficiency of Priority Queue Architectures in FPGA
Efficiency of Priority Queue Architectures in FPGA Open
This paper presents a novel SRAM-based architecture of a data structure that represents a set of multiple priority queues that can be implemented in FPGA or ASIC. The proposed architecture is based on shift registers, systolic arrays and S…
View article: ASIC Architecture and Implementation of RED Scheduler for Mixed- Criticality Real-Time Systems
ASIC Architecture and Implementation of RED Scheduler for Mixed- Criticality Real-Time Systems Open
This paper presents a new ASIC design of a coprocessor that performs process scheduling for embedded mixed-criticality real-time systems consisting of processes of various criticality and various real-time attributes. The proposed solution…
View article: Novel efficient on-chip task scheduler for multi-core hard real-time systems
Novel efficient on-chip task scheduler for multi-core hard real-time systems Open
This article presents an efficient hardware architecture of EDF-based task scheduler, which is suitable for hard real-time systems due to the constant response time of the scheduler. The proposed scheduler contains a queue of ready tasks t…
View article: RED-based Scheduler on Chip for Mixed-Criticality Real-Time Systems
RED-based Scheduler on Chip for Mixed-Criticality Real-Time Systems Open
Real-time embedded systems that combine processes of various criticalities (i.e. mixed-criticality real-time systems) represent an emerging research that faces many issues. This paper describes a new ASIC design of a coprocessor that reali…
View article: Hardware Dynamic Memory Manager for Hard Real-Time Systems
Hardware Dynamic Memory Manager for Hard Real-Time Systems Open
This paper presents novel hardware architecture of dynamic memory manager providing memory allocation and deallocation operations that are suitable for hard real-time and safety-critical systems due to very high determinism of these operat…
View article: Hardware Dynamic Memory Manager for Hard Real-Time Systems
Hardware Dynamic Memory Manager for Hard Real-Time Systems Open
This paper presents novel hardware architecture of dynamic memory manager providing memory allocation and deallocation operations that are suitable for hard real-time and safety-critical systems due to very high determinism of these operat…