Manolis Ploumidis
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View article: The ExaNeSt Prototype: Evaluation of Efficient HPC Communication Hardware in an ARM-based Multi-FPGA Rack
The ExaNeSt Prototype: Evaluation of Efficient HPC Communication Hardware in an ARM-based Multi-FPGA Rack Open
We present and evaluate the ExaNeSt prototype, which compactly packages 128 Xilinx ZU9EG MPSoCs, two TBytes of DRAM, and eight TBytes of SSD into a liquid-cooled rack, using a custom interconnection hardware based on 10 GB/s links. We deve…
View article: Impact of Cache Coherence on the Performance of Shared-Memory based MPI Primitives: A Case Study for Broadcast on Intel Xeon Scalable Processors
Impact of Cache Coherence on the Performance of Shared-Memory based MPI Primitives: A Case Study for Broadcast on Intel Xeon Scalable Processors Open
Recent processor advances have made feasible HPC nodes with high core counts, capable of hosting tens or even, hundreds of processes.Therefore, designing MPI collective operations at the intra-node level has received significant attention …
View article: The ExaNeSt Prototype: Evaluation of Efficient HPC Communication Hardware in an ARM-based Multi-FPGA Rack
The ExaNeSt Prototype: Evaluation of Efficient HPC Communication Hardware in an ARM-based Multi-FPGA Rack Open
We present and evaluate the ExaNeSt Prototype, a liquid-cooled rack prototype consisting of 256 Xilinx ZU9EG MPSoCs, 4 TBytes of DRAM, 16 TBytes of SSD, and configurable interconnection 10-Gbps hardware. We developed this testbed in 2016-2…
View article: Impact of Cache Coherence on the Performance of Shared-Memory based MPI Primitives: A Case Study for Broadcast on Intel Xeon Scalable Processors - Computational Artifacts
Impact of Cache Coherence on the Performance of Shared-Memory based MPI Primitives: A Case Study for Broadcast on Intel Xeon Scalable Processors - Computational Artifacts Open
Collection of computationtal artifacts (source code, scripts, datasets, instructions) for reproducibility of experiments featured in the associated paper: Impact of Cache Coherence on the Performance of Shared-Memory based MPI Primitives: …
View article: Impact of Cache Coherence on the Performance of Shared-Memory based MPI Primitives: A Case Study for Broadcast on Intel Xeon Scalable Processors - Computational Artifacts
Impact of Cache Coherence on the Performance of Shared-Memory based MPI Primitives: A Case Study for Broadcast on Intel Xeon Scalable Processors - Computational Artifacts Open
Collection of computationtal artifacts (source code, scripts, datasets, instructions) for reproducibility of experiments featured in the associated paper: Impact of Cache Coherence on the Performance of Shared-Memory based MPI Primitives: …
View article: Performance of Flow Allocation with Successive Interference Cancelation for Random Access WMNs
Performance of Flow Allocation with Successive Interference Cancelation for Random Access WMNs Open
In this study, we explore the gain that can be achieved by jointly allocating flow on multiple paths and applying successive interference cancelation (SIC), for random access wireless mesh networks with multi-packet reception capabilities.…
View article: Improving the Performance and Resilience of MPI Parallel Jobs with Topology and Fault-Aware Process Placement
Improving the Performance and Resilience of MPI Parallel Jobs with Topology and Fault-Aware Process Placement Open
HPC systems keep growing in size to meet the ever-increasing demand for performance and computational resources. Apart from increased performance, large scale systems face two challenges that hinder further growth: energy efficiency and re…
View article: Towards resilient EU HPC systems: A blueprint
Towards resilient EU HPC systems: A blueprint Open
This document aims to spearhead a Europe-wide discussion on HPC system resilience and to help the European HPC community define best practices for resilience. We analyse a wide range of state-of-the-art resilience mechanisms and recommend …